Instruction Manual

33
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
AC Timing Characteristics – 3.3V Operation AT40KLV
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: V
CC
= 3.00V, temperature = 70°C
Minimum times based on best case: V
CC
= 3.60V, temperature = 0° C
Maximum delays are the average of t
PDLH
and t
PDHL
.
Cell Function Parameter Path -3 Units Notes
Core
2-input Gate t
PD
(Maximum) x/y -> x/y 2.9 ns 1 unit load
3-input Gate t
PD
(Maximum) x/y/z -> x/y 2.8 ns 1 unit load
3-input Gate t
PD
(Maximum) x/y/w -> x/y 3.4 ns 1 unit load
4-input Gate t
PD
(Maximum) x/y/w/z -> x/y 3.4 ns 1 unit load
Fast Carry t
PD
(Maximum) y -> y 2.3 ns 1 unit load
Fast Carry t
PD
(Maximum) x -> y 2.9 ns 1 unit load
Fast Carry t
PD
(Maximum) y -> x 3.0 ns 1 unit load
Fast Carry t
PD
(Maximum) x -> x 2.3 ns 1 unit load
Fast Carry t
PD
(Maximum) w -> y 3.4 ns 1 unit load
Fast Carry t
PD
(Maximum) w -> x 3.4 ns 1 unit load
Fast Carry t
PD
(Maximum) z -> y 3.4 ns 1 unit load
Fast Carry t
PD
(Maximum) z -> x 2.4 ns 1 unit load
DFF t
PD
(Maximum) q -> x/y 2.8 ns 1 unit load
DFF t
PD
(Maximum) R -> x/y 3.2 ns 1 unit load
DFF t
PD
(Maximum) S -> x/y 3.0 ns 1 unit load
DFF t
PD
(Maximum) q -> w 2.7 ns
Incremental -> L t
PD
(Maximum) x/y -> L 2.4 ns 1 unit load
Local Output Enable t
PZX
(Maximum) oe -> L 2.8 ns 1 unit load
Local Output Enable t
PXZ
(Maximum) oe -> L 2.4 ns