Instruction Manual

28
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
AC Timing Characteristics – 5V Operation AT40K
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: V
CC
= 4.75V, temperature = 70°C
Minimum times based on best case: V
CC
= 5.25V, temperature = 0° C
Maximum delays are the average of t
PDLH
and t
PDHL
.
Cell Function Parameter Path -2 Units Notes
Async RAM
Write t
WECYC
(Minimum) cycle time 8.0 ns
Write t
WEL
(Minimum) we 3.0 ns Pulse width low
Write t
WEH
(Minimum) we 3.0 ns Pulse width high
Write t
AWS
(Minimum) wr addr setup -> we 2.0 ns
Write t
AWH
(Minimum) wr addr hold -> we 0.0 ns
Write t
DS
(Minimum) din setup -> we 2.0 ns
Write t
DH
(Minimum) din hold -> we 0.0 ns
Write/Read t
DD
(Maximum) din -> dout 4.6 ns rd addr = wr addr
Read t
AD
(Maximum) rd addr -> dout 3.1 ns
Read t
OZX
(Maximum) oe -> dout 1.6 ns
Read t
OXZ
(Maximum) oe -> dout 2.0 ns
Sync RAM
Write t
CYC
(Minimum) cycle time 8.0 ns
Write t
CLKL
(Minimum) clk 3.0 ns Pulse width low
Write t
CLKH
(Minimum) clk 3.0 ns Pulse width high
Write t
WCS
(Minimum) we setup -> clk 2.0 ns
Write t
WCH
(Minimum) we hold -> clk 0.0 ns
Write t
ACS
(Minimum) wr addr setup -> clk 2.0 ns
Write t
ACH
(Minimum) wr addr hold -> clk 0.0 ns
Write t
DCS
(Minimum) wr data setup -> clk 2.0 ns
Write t
DCH
(Minimum) wr data hold -> clk 0.0 ns
Write/Read t
CD
(Maximum) clk -> dout 3.5 ns rd addr = wr addr
Read t
AD
(Maximum) rd addr -> dout 3.1 ns
Read t
OZX
(Maximum) oe -> dout 1.6 ns
Read t
OXZ
(Maximum) oe -> dout 2.0 ns