Instruction Manual

22
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
Figure 14. Northwest Corner (Similar for NE/SE/SW Corners) AT40K/AT40KLV
CELL
GND
PULL-UP PULL-DOWN
TTL/CMOS
DRIVE
VCC
TRI-STATE
DELAY
SCHMITT
PAD
TTL/CMOS
DRIVE
PULL-UP
VCC
TRI-STATE
PULL-DOWN
GND
DELAY
SCHMITT
PAD
PAD
CELL
TTL/CMOS
DRIVE
PULL-UP
VCC
TRI-STATE
PULL-DOWN
GND
DELAY
SCHMITT
“0”
“1”
“0”
“1”
“0” “1” “0” “1” “0” “1” “0” “1”
CELL