Instruction Manual

21
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
Figure 13. South I/O (Mirrored for North I/O) AT40K/AT40KLV
VCC
TTL/CMOS
GND
PULL-UP
PAD
DRIVE
TRI-STATE
PULL-DOWN
DELAY
SCHMITT
“0”
“1”
“0”
“1”
CELL
CELL
CELL
PAD
GND
PULL-UP
PULL-DOWN
TTL/CMOS
DRIVE
VCC
TRI-STATE
DELAY
SCHMITT
“0”
“1”
“1”
“0”
CELL
CELL
(a) Primary I/O
(a) Secondary I/O
SOURCE SELECT MUX
SOURCE SELECT MUX