Instruction Manual

20
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
Figure 12. West I/O (Mirrored for East I/O) AT40K/AT40KLV
(a) Primary I/O
(b) Secondary I/O
PAD
CELL
CELL
CELL
TTL/CMOS
DRIVE
PULL-UP
VCC
TRI-STATE
PULL-DOWN
GND
DELAY
SCHMITT
“0”
“1”
SOURCE
SELECT MUX
“0”
“1”
PAD
CELL
CELL
PULL-UP
VCC
PULL-DOWN
GND
DRIVE
TRI-STATE
TTL/CMOS
DELAY
SCHMITT
“0”
“1”
“1”
“0”
DELAY
SOURCE
SELECT MUX