15
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
Figure 10. Clocking (for One Column of Cells)
Global Clock Line
(Buried)
Sector Clock Mux
Column Clock Mux
Sector Clock Mux
Express Bus
(Plane 4; Half Length at Edge)
GCK1 - GCK8
Repeater
FCK (2 per Edge Column of the Array)
“1”
“1”
“1”
“1”
}
