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Features

• Serial Peripheral Interface (SPI) Compatible

• Supports SPI Modes 0 (0,0) and 3 (1,1)

– Datasheet describes Mode 0 Operation

• 20 MHz Clock Rate

• Byte Mode and 256-byte Page Mode for Program Operations

• Sector Architecture:

– Eight Sectors with 64K Bytes Each (4M)

– 256 Pages per Sector

• Product Identification Mode

• Low-voltage Operation

– 2.7 (V

= 2.7V to 3.6V)

• Sector Write Protection

– Protect 1/8, 1/4, 1/2 or Entire Array

• Write Protect (WP) Pin and Write Disable Instructions for

both Hardware and Software Data Protection

• Self-timed Program Cycle (30 µs/Byte Typical)

• Self-timed Sector Erase Cycle (1 second/Sector Typical)

• Single Cycle Reprogramming (Erase and Program) for Status Register

• High Reliability

– Endurance: 10,000 Write Cycles Typical

• 8-lead EIAJ SOIC

Description

The AT25F4096 provides 4,194,304 bits of serial reprogrammable Flash memory

organized as 524,288 words of 8 bits each. The device is optimized for use in many

industrial and commercial applications where low-power and low-voltage operation

are essential. The AT25F4096 is available in a space-saving 8-lead EIAJ SOIC

package.

SPI Serial

Memory

4M (524,288 x 8)

AT25F4096

Advance

Information

2454C–SEEPR–8/04

Pin Configurations

Pin Name Function

Chip Select

SCK Serial Data Clock

SI Serial Data Input

SO Serial Data Output

GND Ground

VCC Power Supply

Write Protect

HOLD

Suspends Serial Input

8-lead EIAJ SOIC

GND

VCC

HOLD

SCK

Summary of content (17 pages)

PAGE 1
Features • Serial Peripheral Interface (SPI) Compatible • Supports SPI Modes 0 (0,0) and 3 (1,1) – Datasheet describes Mode 0 Operation • 20 MHz Clock Rate • Byte Mode and 256-byte Page Mode for Program Operations • Sector Architecture: • • • • • • • • • – Eight Sectors with 64K Bytes Each (4M) – 256 Pages per Sector Product Identification Mode Low-voltage Operation – 2.7 (VCC = 2.7V to 3.
PAGE 2
The AT25F4096 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All write cycles are completely self-timed. BLOCK WRITE protection for top 1/8, top 1/4, top 1/2 or the entire memory array is enabled by programming the status register. Separate write enable and write disable instructions are provided for additional data protection.
PAGE 3
AT25F4096 [Advance Information] Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +3.6V (unless otherwise noted). Symbol Test Conditions COUT Output Capacitance (SO) CIN Note: Max Units Conditions 8 pF VOUT = 0V 6 pF VIN = 0V Input Capacitance (CS, SCK, SI, WP, HOLD) 1. This parameter is characterized and is not 100% tested.
PAGE 4
AC Characteristics (Preliminary – Subject to Change) Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +2.7V to +3.6V CL = 1 TTL Gate and 30 pF (unless otherwise noted).
PAGE 5
AT25F4096 [Advance Information] Serial Interface Description MASTER: The device that generates the serial clock. SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25F4096 always operates as a slave. TRANSMITTER/RECEIVER: The AT25F4096 has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received.
PAGE 6
SPI Serial Interface MASTER: MICROCONTROLLER DATA OUT (MOSI) DATA IN (MISO) SERIAL CLOCK (SPI CK) SS0 SS1 SS2 SS3 SLAVE: AT25F4096 SI SO SCK CS SI SO SCK CS SI SO SCK CS SI SO SCK CS 6 AT25F4096 [Advance Information] 2454C–SEEPR–8/04
PAGE 7
AT25F4096 [Advance Information] Functional Description The AT25F4096 is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 6800 type series of microcontrollers. The AT25F4096 utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table 1. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low transition. Write is defined as program and/or erase in this specification.
PAGE 8
Table 3. Read Status Register Bit Definition Bit Definition Bit 0 (RDY) Bit 0 = 0 (RDY) indicates the device is READY. Bit 0 = 1 indicates the write cycle is in progress. Bit 1 (WEN) Bit 1 = 0 indicates the device is not WRITE ENABLED. Bit 1 = 1 indicates the device is WRITE ENABLED. Bit 2 (BP0) See Table 4. Bit 3 (BP1) See Table 4. Bit 4 (BP2) See Table 4. Bits 5-6 are 0s when device is not in an internal write cycle. Bit 7 (WPEN) See Table 5. Bits 0-7 are 1s during an internal write cycle.
PAGE 9
AT25F4096 [Advance Information] order to write the status register, the device must first be write enabled via the WREN instruction. Then, the instruction and data for the four bits are entered. During the internal write cycle, all instructions will be ignored except RDSR instructions. The AT25F4096 will automatically return to write disable state at the completion of the WRSR cycle. Note: When the WPEN bit is hardware write protected, it cannot be changed back to “0”, as long as the WP pin is held low.
PAGE 10
first. The AT25F4096 will automatically return to the write disable state at the completion of the PROGRAM cycle. Note: If the device is not write enabled (WREN), the device will ignore the Write instruction and will return to the standby state, when CS is brought high. A new CS falling edge is required to re-initiate the serial communication. Table 6.
PAGE 11
AT25F4096 [Advance Information] Timing Diagrams (for SPI Mode 0 (0, 0)) Synchronous Data Timing t CS VIH CS VIL t CSH t CSS VIH t WH SCK t WL VIL tH t SU VIH SI VALID IN VIL tV VOH SO HI-Z t HO t DIS HI-Z VOL WREN Timing WRDI Timing 11 2454C–SEEPR–8/04
PAGE 12
RDSR Timing CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2 1 0 SCK INSTRUCTION SI DATA OUT HIGH IMPEDANCE SO 7 6 5 4 3 MSB WRSR Timing READ Timing CS 0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 32 33 34 35 36 37 38 39 SCK 3-BYTE ADDRESS SI SO 12 INSTRUCTION 23 22 21 ...
PAGE 13
AT25F4096 [Advance Information] PROGRAM Timing 4 5 6 7 8 9 10 11 28 29 30 31 32 33 34 2079 3 2078 2 2077 1 2076 0 2075 CS SCK 256th BYTE DATA-IN 1st BYTE DATA-IN 3-BYTE ADDRESS SI INSTRUCTION 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0 HIGH IMPEDANCE SO HOLD Timing CS tCD tCD SCK tHD tHD HOLD tHZ SO tLZ SECTOR ERASE Timing X X = Don’t Care bit 13 2454C–SEEPR–8/04
PAGE 14
CHIP ERASE Timing X X = Don’t Care bit RDID Timing CS 4 5 6 7 8 1 X 1 0 1 0 1 2 3 0 0 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK SI SO 14 0 HIGH IMPEDANCE MANUFACTURER 7 CODE (ATMEL) DATA OUT 5 4 3 2 DEVICE CODE 6 1 0 AT25F4096 [Advance Information] 2454C–SEEPR–8/04
PAGE 15
AT25F4096 [Advance Information] Ordering Information Ordering Code Package AT25F4096W-10SU-2.7 8S2 Operation Range Lead-Free/Halogen-Free/ Industrial Temperature (-40°C to 85°C) Package Type 8S2 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) Options -2.7 Low Voltage (2.7V to 3.
PAGE 16
Package Information 8S2 – EIAJ SOIC C 1 E E1 L N Top View ∅ End View e b COMMON DIMENSIONS (Unit of Measure = mm) A SYMBOL A1 D Side View NOM MAX NOTE 1.70 2.16 A1 0.05 0.25 b 0.35 0.48 5 C 0.15 0.35 5 D 5.13 5.35 E1 5.18 5.40 E 7.70 8.26 L 0.51 0.85 ∅ 0˚ 8˚ e Notes: 1. 2. 3. 4. 5. MIN A 2, 3 1.27 BSC 4 This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
PAGE 17
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg.