Owner's manual

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Features

• Serial Peripheral Interface (SPI) Compatible

• Supports SPI Modes 0 (0,0) and 3 (1,1)

• 20 MHz Clock Rate

• Byte Mode and 256-byte Page Mode for Program Operations

• Sector Architecture:

– Four Sectors with 64K Bytes Each

– 256 Pages per Sector

• Product Identification Mode

• Low-voltage Operation

– 2.7 (V

= 2.7V to 3.6V)

• Sector Write Protection

– Protect 1/4, 1/2 or Entire Array

• Write Protect (WP) Pin and Write Disable Instructions for

both Hardware and Software Data Protection

• Self-timed Program Cycle (30 µs/Byte Typical)

• Self-timed Sector Erase Cycle (1 second/Sector Typical)

• Single Cycle Reprogramming (Erase and Program) for Status Register

• High Reliability

– Endurance: 10,000 Write Cycles Typical

• 8-lead JEDEC SOIC

Description

The AT25F2048 provides 2,097,152 bits of serial reprogrammable Flash memory

organized as 262,144 words of 8 bits each. The device is optimized for use in many

industrial and commercial applications where low-power and low-voltage operation

are essential. The AT25F2048 is available in a space-saving 8-lead JEDEC SOIC

package.

Rev. 2455D–SEEPR–7/04

SPI Serial

Memory

2M (262,144 x 8)

AT25F2048

Preliminary

Pin Configurations

Pin Name Function

Chip Select

SCK Serial Data Clock

SI Serial Data Input

SO Serial Data Output

GND Ground

VCC Power Supply

Write Protect

HOLD

Suspends Serial Input

8-lead SOIC

GND

VCC

HOLD

SCK

Summary of content (17 pages)

PAGE 1
Features • • • • • • • • • • • • • • Serial Peripheral Interface (SPI) Compatible Supports SPI Modes 0 (0,0) and 3 (1,1) 20 MHz Clock Rate Byte Mode and 256-byte Page Mode for Program Operations Sector Architecture: – Four Sectors with 64K Bytes Each – 256 Pages per Sector Product Identification Mode Low-voltage Operation – 2.7 (VCC = 2.7V to 3.
PAGE 2
The AT25F2048 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All write cycles are completely self-timed. BLOCK WRITE protection for top 1/4, top 1/2 or the entire memory array is enabled by programming the status register. Separate write enable and write disable instructions are provided for additional data protection.
PAGE 3
AT25F2048 Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +3.6V (unless otherwise noted). Symbol Test Conditions COUT Output Capacitance (SO) CIN Note: Max Units Conditions 8 pF VOUT = 0V 6 pF VIN = 0V Input Capacitance (CS, SCK, SI, WP, HOLD) 1. This parameter is characterized and is not 100% tested. DC Characteristics (Preliminary – Subject to Change) Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +2.7V to +3.
PAGE 4
AC Characteristics (Preliminary – Subject to Change) Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +2.7V to +3.6V CL = 1 TTL Gate and 30 pF (unless otherwise noted).
PAGE 5
AT25F2048 Serial Interface Description MASTER: The device that generates the serial clock. SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25F2048 always operates as a slave. TRANSMITTER/RECEIVER: The AT25F2048 has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received.
PAGE 6
SPI Serial Interface MASTER: MICROCONTROLLER DATA OUT (MOSI) DATA IN (MISO) SERIAL CLOCK (SPI CK) SS0 SS1 SS2 SS3 SLAVE: AT25F2048 SI SO SCK CS SI SO SCK CS SI SO SCK CS SI SO SCK CS 6 AT25F2048 2455D–SEEPR–7/04
PAGE 7
AT25F2048 Functional Description The AT25F2048 is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 6800 type series of microcontrollers. The AT25F2048 utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table 1. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low transition. Write is defined as program and/or erase in this specification.
PAGE 8
Table 3. Read Status Register Bit Definition Bit Definition Bit 0 (RDY) Bit 0 = 0 (RDY) indicates the device is READY. Bit 0 = 1 indicates the write cycle is in progress. Bit 1 (WEN) Bit 1 = 0 indicates the device is not WRITE ENABLED. Bit 1 = 1 indicates the device is WRITE ENABLED. Bit 2 (BP0) See Table 4. Bit 3 (BP1) See Table 4. Bits 4-6 are 0s when device is not in an internal write cycle. Bit 7 (WPEN) See Table 5. Bits 0-7 are 1s during an internal write cycle.
PAGE 9
AT25F2048 The WRSR instruction also allows the user to enable or disable the Write Protect (WP) pin through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN bit is “1”. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is “0.
PAGE 10
A single PROGRAM instruction programs 1 to 256 consecutive bytes within a page if it is not write protected. The starting byte could be anywhere within the page. When the end of the page is reached, the address will wrap around to the beginning of the same page. If the data to be programmed are less than a full page, the data of all other bytes on the same page will remain unchanged.
PAGE 11
AT25F2048 Timing Diagrams (for SPI Mode 0 (0, 0)) Synchronous Data Timing t CS VIH CS VIL t CSH t CSS VIH t WH SCK t WL VIL tH t SU VIH SI VALID IN VIL tV VOH SO HI-Z t HO t DIS HI-Z VOL WREN Timing WRDI Timing 11 2455D–SEEPR–7/04
PAGE 12
RDSR Timing CS 0 1 2 3 4 5 6 7 8 9 10 7 6 5 11 12 13 14 15 2 1 0 SCK INSTRUCTION SI DATA OUT HIGH IMPEDANCE SO 4 3 MSB WRSR Timing READ Timing CS 0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 32 33 34 35 36 37 38 39 SCK 3-BYTE ADDRESS SI SO 12 INSTRUCTION HIGH IMPEDANCE 23 22 21 ...
PAGE 13
AT25F2048 PROGRAM Timing 4 5 6 7 8 9 10 11 28 29 30 31 32 33 34 2079 3 2078 2 2077 1 2076 0 2075 CS SCK 256th BYTE DATA-IN 1st BYTE DATA-IN 3-BYTE ADDRESS SI INSTRUCTION 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0 HIGH IMPEDANCE SO HOLD Timing CS tCD tCD SCK tHD tHD HOLD tHZ SO tLZ SECTOR ERASE Timing X X = Don’t Care bit 13 2455D–SEEPR–7/04
PAGE 14
CHIP ERASE Timing X X = Don’t Care bit RDID Timing 12 13 14 15 16 17 18 19 X MANUFACTURER CODE (ATMEL) 14 DEVICE CODE AT25F2048 2455D–SEEPR–7/04
PAGE 15
AT25F2048 Ordering Information Ordering Code Package AT25F2048N-10SU-2.7 8S1 Operation Range Industrial (-40°C to 85°C) Package Type 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) Options -2.7 Low Voltage (2.7V to 3.
PAGE 16
Package Information 8S1 – JEDEC SOIC C 1 E E1 L N ∅ Top View End View e B COMMON DIMENSIONS (Unit of Measure = mm) A A1 D Side View SYMBOL MIN NOM MAX A 1.35 – 1.75 A1 0.10 – 0.25 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.00 E1 3.81 – 3.99 E 5.79 – 6.20 e NOTE 1.27 BSC L 0.40 – 1.27 ∅ 0˚ – 8˚ Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
PAGE 17
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg.