User guide

49
AT25DL161 [DATASHEET]
8795E–DFLASH–12/2012
14.4 AC Characteristics – Maximum Clock Frequencies
14.5 AC Characteristics – All Other Parameters
Notes: 1. Not 100% tested (value guaranteed by design and characterization).
2. 15pF load at frequencies above 70MHz, 30pF otherwise.
3. Only applicable as a constraint for the Write Status Register Byte 1 command when SPRL = 1.
Symbol Parameter Min Max Units
RapidS and SPI Operation
f
MAX
Maximum clock frequency for all operations – RapidS operation only
(excluding 03h, 0Bh, 3Bh, and 9Fh opcodes)
100 MHz
f
CLK
Maximum clock frequency for all operations (excluding 03h opcode) 85 MHz
f
RDLF
Maximum clock frequency for 03h opcode (Read Array – Low Frequency) 40 MHz
f
RDDO
Maximum clock frequency for 3Bh opcode (Dual-Output Read) 66 MHz
Symbol Parameter Min Max Units
t
CLKH
Clock High Time 4.3 ns
t
CLKL
Clock Low Time 4.3 ns
t
CLKR
(1)
Clock Rise Time, Peak-to-peak (Slew Rate) 0.1 V/ns
t
CLKF
(1)
Clock Fall Time, Peak-to-peak (Slew Rate) 0.1 V/ns
t
CSH
Chip Select High Time 30 ns
t
CSLS
Chip Select Low Setup Time (Relative to Clock) 5 ns
t
CSLH
Chip Select Low Hold Time (Relative to Clock) 5 ns
t
CSHS
Chip Select High Setup Time (Relative to Clock) 5 ns
t
CSHH
Chip Select High Hold Time (Relative to Clock) 5 ns
t
DS
Data in Setup Time 2 ns
t
DH
Data in Hold Time 1 ns
t
DIS
(1)
Output Disable Time 5 ns
t
V
(2)
Output Valid Time 5 ns
t
OH
Output Hold Time 2 ns
t
HLS
HOLD Low Setup Time (Relative to Clock) 5 ns
t
HLH
HOLD Low Hold Time (Relative to Clock) 5 ns
t
HHS
HOLD High Setup Time (Relative to Clock) 5 ns
t
HHH
HOLD High Hold Time (Relative to Clock) 5 ns
t
HLQZ
(1)
HOLD Low to Output High-Z 5 ns
t
HHQX
(1)
HOLD High to Output Low-Z 5 ns
t
WPS
(1)(3)
Write Protect Setup Time 20 ns
t
WPH
(1)(3)
Write Protect Hold Time 100 ns
t
SECP
(1)
Sector Protect Time (from Chip Select High) 20 ns
t
SECUP
(1)
Sector Unprotect Time (from Chip Select High) 20 ns
t
LOCK
(1)
Sector Lockdown and Freeze Sector Lockdown State Time (from Chip Select High) 200 μs
t
EDPD
(1)
Chip Select High to Deep Power-Down 3 μs
t
RDPD
(1)
Chip Select High to Standby Mode 35 μs
t
RST
Reset Time 30 μs