Features • Single 2.7V - 3.
1. Description The Adesto® AT25DF081A is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The flexible erase architecture of the AT25DF081A, with its erase granularity as small as 4-Kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage EEPROM devices.
AT25DF081A 2. Pin Descriptions and Pinouts Table 2-1. Pin Descriptions Asserted State Type Low Input SCK SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the flow of data to and from the device. Command, address, and input data present on the SI pin is always latched in on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling edge of SCK.
Table 2-1. Pin Descriptions (Continued) Asserted State Type DEVICE POWER SUPPLY: The VCC pin is used to supply the source voltage to the device. Operations at invalid VCC voltages may produce spurious results and should not be attempted. - Power GROUND: The ground reference for the power supply. GND should be connected to the system ground. - Power Symbol Name and Function VCC GND Figure 2-1.
AT25DF081A 4. Memory Array To provide the greatest flexibility, the memory array of the AT25DF081A can be erased in four levels of granularity including a full chip erase. In addition, the array has been divided into physical sectors of uniform size, of which each sector can be individually protected from program and erase operations. The size of the physical sectors is optimized for both code and data storage applications, allowing both code and data segments to reside in their own isolated regions.
5. Device Operation The AT25DF081A is controlled by a set of instructions that are sent from a host controller, commonly referred to as the SPI Master. The SPI Master communicates with the AT25DF081A via the SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO). The AT25DF081A features a dual-input program mode in which the SO pin becomes an input.
AT25DF081A Table 6-1.
7. Read Commands 7.1 Read Array The Read Array command can be used to sequentially read a continuous stream of data from the device by simply providing the clock signal once the initial starting address has been specified. The device incorporates an internal address counter that automatically increments on every clock cycle. Three opcodes (1Bh, 0Bh, and 03h) can be used for the Read Array command.
AT25DF081A Figure 7-2. Read Array – 0Bh Opcode CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 SCK OPCODE SI 0 0 0 0 1 ADDRESS BITS A23-A0 0 1 1 MSB A A A A A A A DON'T CARE A A MSB X X X X X X X X MSB DATA BYTE 1 SO HIGH-IMPEDANCE D D MSB Figure 7-3.
7.2 Dual-Output Read Array The Dual-Output Read Array command is similar to the standard Read Array command and can be used to sequentially read a continuous stream of data from the device by simply providing the clock signal once the initial starting address has been specified. Unlike the standard Read Array command, however, the Dual-Output Read Array command allows two bits of data to be clocked out of the device on every clock cycle rather than just one.
AT25DF081A 8. Program and Erase Commands 8.1 Byte/Page Program The Byte/Page Program command allows anywhere from a single byte of data to 256-bytes of data to be programmed into previously erased memory locations. An erased memory location is one that has all eight bits set to the logical “1” state (a byte value of FFh).
Figure 8-1. Byte Program CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 SCK OPCODE SI 0 0 0 0 0 ADDRESS BITS A23-A0 0 1 A 0 MSB SO Figure 8-2.
AT25DF081A 8.2 Dual-Input Byte/Page Program The Dual-Input Byte/Page Program command is similar to the standard Byte/Page Program command and can be used to program anywhere from a single byte of data up to 256-bytes of data into previously erased memory locations. Unlike the standard Byte/Page Program command, however, the Dual-Input Byte/Page Program command allows two bits of data to be clocked into the device on every clock cycle rather than just one.
Figure 8-3. Dual-Input Byte Program CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 SCK OPCODE SI 1 0 1 0 0 0 1 0 MSB SOI INPUT DATA BYTE ADDRESS BITS A23-A0 A A A A A A A A A D6 D4 D2 D0 MSB HIGH-IMPEDANCE D7 D5 D3 D1 MSB Figure 8-4.
AT25DF081A 8.3 Block Erase A block of 4-, 32-, or 64-Kbytes can be erased (all bits set to the logical “1” state) in a single operation by using one of three different opcodes for the Block Erase command. An opcode of 20h is used for a 4-Kbyte erase, an opcode of 52h is used for a 32-Kbyte erase, and an opcode of D8h is used for a 64-Kbyte erase.
8.4 Chip Erase The entire memory array can be erased in a single operation by using the Chip Erase command. Before a Chip Erase command can be started, the Write Enable command must have been previously issued to the device to set the WEL bit of the Status Register to a logical “1” state. Two opcodes, 60h and C7h, can be used for the Chip Erase command. There is no difference in device functionality when utilizing the two opcodes, so they can be used interchangeably.
AT25DF081A 9. Protection Commands and Features 9.1 Write Enable The Write Enable command is used to set the Write Enable Latch (WEL) bit in the Status Register to a logical “1” state. The WEL bit must be set before a Byte/Page Program, erase, Protect Sector, Unprotect Sector, Sector Lockdown, Freeze Sector Lockdown State, Program OTP Security Register, or Write Status Register command can be executed.
9.2 Write Disable The Write Disable command is used to reset the Write Enable Latch (WEL) bit in the Status Register to the logical "0" state. With the WEL bit reset, all Byte/Page Program, erase, Protect Sector, Unprotect Sector, Sector Lockdown, Freeze Sector Lockdown State, Program OTP Security Register, and Write Status Register commands will not be executed. Other conditions can also cause the WEL bit to be reset; for more details, refer to the WEL bit section of the Status Register description.
AT25DF081A 9.3 Protect Sector Every physical 64-Kbyte sector of the device has a corresponding single-bit Sector Protection Register that is used to control the software protection of a sector. Upon device power-up, each Sector Protection Register will default to the logical “1” state indicating that all sectors are protected and cannot be programmed or erased. Issuing the Protect Sector command to a particular sector address will set the corresponding Sector Protection Register to the logical “1” state.
9.4 Unprotect Sector Issuing the Unprotect Sector command to a particular sector address will reset the corresponding Sector Protection Register to the logical “0” state (see Table 9-1 for Sector Protection Register values). Every physical sector of the device has a corresponding single-bit Sector Protection Register that is used to control the software protection of a sector.
AT25DF081A 9.5 Global Protect/Unprotect The Global Protect and Global Unprotect features can work in conjunction with the Protect Sector and Unprotect Sector functions. For example, a system can globally protect the entire memory array and then use the Unprotect Sector command to individually unprotect certain sectors and individually reprotect them later by using the Protect Sector command.
Table 9-2. WP State Valid SPRL and Global Protect/Unprotect Conditions (Continued) Current SPRL Value New Write Status Register Byte 1 Data Bit 76543210 0x0000xx 0x0001xx 0x1110xx 0x1111xx 1 1 1x0000xx 1x0001xx 1x1110xx 1x1111xx New SPRL Value Protection Operation No change to the current protection level. All sectors currently protected will remain protected, and all sectors currently unprotected will remain unprotected.
AT25DF081A 9.6 Read Sector Protection Registers The Sector Protection Registers can be read to determine the current software protection status of each sector. Reading the Sector Protection Registers, however, will not determine the status of the WP pin. To read the Sector Protection Register for a particular sector, the CS pin must first be asserted and the opcode of 3Ch must be clocked in.
9.7 Protected States and the Write Protect (WP) Pin The WP pin is not linked to the memory array itself and has no direct effect on the protection status or lockdown status of the memory array. Instead, the WP pin, in conjunction with the SPRL (Sector Protection Registers Locked) bit in the Status Register, is used to control the hardware locking mechanism of the device.
AT25DF081A 10. Security Commands 10.1 Sector Lockdown Certain applications require that portions of the Flash memory array be permanently protected against malicious attempts at altering program code, data modules, security information, or encryption/decryption algorithms, keys, and routines. To address these applications, the device incorporates a sector lockdown mechanism that allows any combination of individual 64-Kbyte sectors to be permanently locked so that they become read only.
Figure 10-1. Sector Lockdown CS 0 1 2 3 4 5 6 7 8 9 29 30 31 32 33 34 35 36 37 38 39 SCK OPCODE SI 0 0 1 1 0 ADDRESS BITS A23-A0 0 1 1 MSB SO 10.
AT25DF081A 10.3 Read Sector Lockdown Registers The Sector Lockdown Registers can be read to determine the current lockdown status of each physical 64-Kbyte sector. To read the Sector Lockdown Register for a particular 64-Kbyte sector, the CS pin must first be asserted and the opcode of 35h must be clocked in. Once the opcode has been clocked in, three address bytes designating any address within the 64-Kbyte sector must be clocked in.
10.4 Program OTP Security Register The device contains a specialized OTP (One-Time Programmable) Security Register that can be used for purposes such as unique device serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc. The OTP Security Register is independent of the main Flash memory array and is comprised of a total of 128-bytes of memory divided into two portions.
AT25DF081A The three address bytes and at least one complete byte of data must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation and the user-programmable portion of the OTP Security Register will not be programmed.
10.5 Read OTP Security Register The OTP Security Register can be sequentially read in a similar fashion to the Read Array operation up to the maximum clock frequency specified by fMAX. To read the OTP Security Register, the CS pin must first be asserted and the opcode of 77h must be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the starting address location of the first byte to read within the OTP Security Register.
AT25DF081A 11. Status Register Commands 11.1 Read Status Register The two-byte Status Register can be read to determine the device’s ready/busy status, as well as the status of many other functions such as Hardware Locking and Software Protection. The Status Register can be read at any time, including during an internally self-timed program or erase operation. To read the Status Register, the CS pin must first be asserted and the opcode of 05h must be clocked into the device.
Table 11-2.
AT25DF081A 11.1.3 WPP Bit The WPP bit can be read to determine if the WP pin has been asserted or not. 11.1.4 SWP Bits The SWP bits provide feedback on the software protection status for the device. There are three possible combinations of the SWP bits that indicate whether none, some, or all of the sectors have been protected using the Protect Sector command or the Global Protect feature.
11.1.7 SLE Bit The SLE bit is used to enable and disable the Sector Lockdown and Freeze Sector Lockdown State commands. When the SLE bit is in the logical “0” state (the default state after power-up), the Sector Lockdown and Freeze Sector Lockdown commands are disabled. If the Sector Lockdown and Freeze Sector Lockdown commands are disabled, then any attempts to issue the commands will be ignored. This provides a safeguard for these commands against accidental or erroneous execution.
AT25DF081A 11.2 Write Status Register Byte 1 The Write Status Register Byte 1 command is used to modify the SPRL bit of the Status Register and/or to perform a Global Protect or Global Unprotect operation. Before the Write Status Register Byte 1 command can be issued, the Write Enable command must have been previously issued to set the WEL bit in the Status Register to a logical “1”.
11.3 Write Status Register Byte 2 The Write Status Register Byte 2 command is used to modify the RSTE and SLE bits of the Status Register. Using the Write Status Register Byte 2 command is the only way to modify the RSTE and SLE bits in the Status Register during normal device operation, and the SLE bit can only be modified if the sector lockdown state has not been frozen.
AT25DF081A 12. Other Commands and Functions 12.1 Reset In some applications, it may be necessary to prematurely terminate a program or erase cycle early rather than wait the hundreds of microseconds or milliseconds necessary for the program or erase operation to complete normally. The Reset command allows a program or erase operation in progress to be ended abruptly and returns the device to an idle state.
12.2 Read Manufacturer and Device ID Identification information can be read from the device to enable systems to electronically query and identify the device while it is in system. The identification method and the command opcode comply with the JEDEC standard for “Manufacturer and Device ID Read Methodology for SPI Compatible Serial Interface Memory Devices”.
AT25DF081A Figure 12-2. Read Manufacturer and Device ID &6 6&. OPCODE 6, )K +,*+ ,03('$1&( 62 Note: Each transition 12.
Figure 12-3. Deep Power-Down CS tEDPD 0 1 2 3 4 5 6 7 SCK OPCODE SI 1 0 1 1 1 0 0 1 MSB SO HIGH-IMPEDANCE Active Current ICC Standby Mode Current 12.4 Deep Power-Down Mode Current Resume from Deep Power-Down In order to exit the Deep Power-Down mode and resume normal device operation, the Resume from Deep PowerDown command must be issued. The Resume from Deep Power-Down command is the only command that the device will recognized while in the Deep Power-Down mode.
AT25DF081A 12.5 Hold The HOLD pin is used to pause the serial communication with the device without having to stop or reset the clock sequence. The Hold mode, however, does not have an affect on any internally self-timed operations such as a program or erase cycle. Therefore, if an erase cycle is in progress, asserting the HOLD pin will not pause the operation, and the erase cycle will continue until it is finished. The Hold mode can only be entered while the CS pin is asserted.
13. RapidS Implementation To implement RapidS and operate at clock frequencies higher than what can be achieved in a viable SPI implementation, a full clock cycle can be used to transmit data back and forth across the serial bus. The AT25DF081A is designed to always clock its data out on the falling edge of the SCK signal and clock data in on the rising edge of SCK.
AT25DF081A 14. Electrical Specifications 14.1 Absolute Maximum Ratings* Temperature under Bias........................-55°C to +125°C *NOTICE: Storage Temperature ............................-65°C to +150°C All Input Voltages (including NC Pins) with Respect to Ground............................-0.6V to +4.1V All Output Voltages with Respect to Ground....................-0.6V to VCC + 0.5V 14.2 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
14.4 AC Characteristics – Maximum Clock Frequencies Symbol Parameter Min Max Units RapidS and SPI Operation 14.
AT25DF081A 14.6 Program and Erase Characteristics Symbol Parameter tPP(1) Page Program Time (256-Bytes) tBP Byte Program Time tBLKE(1) tCHPE tOTPP(1) Notes: (2) Typ Max Units 1.0 3.0 ms 7 µs 4-Kbytes 50 200 32-Kbytes 250 600 64-Kbytes 400 950 Chip Erase Time 16 28 sec OTP Security Register Program Time 200 500 µs 200 ns Max Units Block Erase Time (1)(2) tWRSR Min Write Status Register Time ms 1.
15. AC Waveforms Figure 15-1. Serial Input Timing tCSH CS tCSLH tCLKL tCSLS tCLKH tCSHH tCSHS SCK tDS SI SO tDH MSB LSB MSB HIGH-IMPEDANCE Figure 15-2. Serial Output Timing CS tCLKH tCLKL tDIS SCK SI tOH tV tV SO Figure 15-3.
AT25DF081A Figure 15-4. HOLD Timing – Serial Input CS SCK tHHH tHLS tHLH tHHS tHLH tHHS HOLD SI SO HIGH-IMPEDANCE Figure 15-5.
16. Ordering Information 16.1 Code Detail Detail AT 2 5 D F 0 8 1 A - S S H - B Designator Shipping Carrier Option B = Bulk (tubes) Y = Bulk (trays) T = Tape and reel Product Family Device Grade H = Green, NiPdAu lead finish, industrial temperature range (-40°C to +85°C) Device Density 8 = 8-megabit Interface Package Option 1 = Serial 16.2 SS = 8-lead, 0.150" wide SOIC S = 8-lead, 0.208" wide SOIC M = 8-pad, 5 x 6 x 0.
AT25DF081A 17. Packaging Information 17.1 8MA1 – UDFN E C Pin 1 ID SIDE VIEW D y TOP VIEW A1 A K E2 0.45 8 Option A Pin #1 Chamfer (C 0.35) 1 Pin #1 Notch (0.20 R) (Option B) 7 2 e D2 6 3 5 4 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 0.45 0.55 0.60 A1 0.00 0.02 0.05 b 0.35 0.40 0.48 C b L BOTTOM VIEW NOTE 0.152 REF D 4.90 5.00 5.10 D2 3.80 4.00 4.20 E 5.90 6.00 6.10 E2 3.20 3.40 3.60 e 1.27 L 0.50 0.60 0.75 y 0.00 – 0.
17.2 8S1 – JEDEC SOIC C 1 E E1 L N Ø TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A A1 D SIDE VIEW Notes: This drawing is for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. SYMBOL MIN A 1.35 NOM MAX – 1.75 A1 0.10 – 0.25 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.05 E1 3.81 – 3.99 E 5.79 – 6.20 e NOTE 1.27 BSC L 0.40 – 1.
AT25DF081A 17.3 8S2 – EIAJ SOIC C 1 E E1 L N q TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A SYMBOL A1 D SIDE VIEW MAX NOM 1.70 2.16 A1 0.05 0.25 NOTE b 0.35 0.48 4 C 0.15 0.35 4 D 5.13 5.35 E1 5.18 5.40 E 7.70 8.26 L 0.51 0.85 q 0° e Notes: 1. 2. 3. 4. MIN A 2 8° 1.27 BSC 3 This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
18. 52 Revision History Doc. Rev. Date Comments 8715C 11/2012 Update to Adesto logos.
Corporate Office California | USA Adesto Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: (+1) 408.400.0578 Email: contact@adestotech.com © 2012 Adesto Technologies. All rights reserved. / Rev.: 8715C–SFLSH–11/2012 Adesto®, the Adesto logo, CBRAM®, and DataFlash® are registered trademarks or trademarks of Adesto Technologies. All other marks are the property of their respective owners.
