10
AT25128A/256A [Preliminary]
3404A–SEEPR–10/03
Timing Diagrams (for SPI Mode 0 (0, 0))
Synchronous Data Timing
WREN Timing
WRDI Timing
SO
V
OH
V
OL
HI-Z
HI-Z
t
V
VALID IN
SI
V
IH
V
IL
t
H
t
SU
t
DIS
SCK
V
IH
V
IL
t
WH
t
CSH
CS
V
IH
V
IL
t
CSS
t
CS
t
WL
t
HO
