Manual

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Features

• Low Voltage and Standard Voltage Operation

–2.7(V

=2.7Vto5.5V)

–1.8(V

=1.8Vto5.5V)

• Internally Organized 2048 x 8 (16K)

• 2-Wire Serial Interface

• Schmitt Trigger, Filtered Inputs for Noise Suppression

• Bidirectional Data Transfer Protocol

• 100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Compatibility

• Write Protect Pin for Hardware Data Protection

• Cascadable Feature Allows for Extended Densities

• 16-Byte Page Write Mode

• PartialPageWritesAreAllowed

• Self-Timed Write Cycle (10 ms max)

• High Reliability

– Endurance: 1 Million Write Cycles

– Data Retention: 100 Years

• Automotive Grade and Extended Temperature Devices Available

• 8-lead PDIP and 8-lead JEDEC SOIC Packages

Description

The AT24C164 provides 16,384 bits of serial electrically erasable and programmable

read only memory (EEPROM) organized as 2048 words of 8 bits each. The device’s

cascadable feature allows up to eight devices to share a common 2-wire bus. The

device is optimized for use in many industrial and commercial applications where low

power and low voltage operation are essential. The AT24C164 is available in space

saving 8-lead PDIP and 8-lead JEDEC SOIC packages and is accessed via a 2-wire

serial interface. In addition, this device is available in 2.7V (2.7V to 5.5V) and 1.8V

(1.8V to 5.5V) versions.

2-Wire Serial

EEPROM

16K (2048 x 8)

AT24C164

Rev. 0105F–SEEPR–08/02

Pin Configurations

Pin Name Function

A0 - A2 Address Inputs

SDA Serial Data

SCL Serial Clock Input

WP Write Protect

8-lead PDIP

GND

VCC

SCL

SDA

8-lead SOIC

GND

VCC

SCL

SDA

Summary of content (16 pages)

PAGE 1
Features • Low Voltage and Standard Voltage Operation • • • • • • • • • • • • • – 2.7 (VCC = 2.7V to 5.5V) – 1.8 (VCC = 1.8V to 5.5V) Internally Organized 2048 x 8 (16K) 2-Wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol 100 kHz (1.8V, 2.5V, 2.
PAGE 2
Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
PAGE 3
AT24C164 Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices. DEVICE SELECT (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that may be hardwired or actively driven to VDD or VSS.
PAGE 4
Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V. Symbol Test Condition CI/O CIN Note: Max Units Conditions Input/Output Capacitance (SDA) 8 pF VI/O = 0V Input Capacitance (A 0, A1, A2, SCL) 6 pF VIN = 0V 1. This parameter is characterized and is not 100% tested. DC Characteristics Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C, VCC = +1.8V to +5.
PAGE 5
AT24C164 AC Characteristics Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted). 2.7-, 2.5-, 1.8-volt Symbol Parameter Min fSCL Clock Frequency, SCL tLOW Clock Pulse Width Low tHIGH Clock Pulse Width High Max 5.0-volt Min 100 Max Units 400 kHz 4.7 1.2 µs 4.0 0.6 µs (1) tI Noise Suppression Time tAA Clock Low to Data Out Valid 0.
PAGE 6
Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing diagram).
PAGE 7
AT24C164 Bus Timing SCL: Serial Clock, SDA: Serial Data I/O Write Cycle Timing SCL: Serial Clock, SDA: Serial Data I/O (1) Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
PAGE 8
Data Validity Start and Stop Definition Output Acknowledge 8 AT24C164 0105F–SEEPR–08/02
PAGE 9
AT24C164 Device Addressing The AT24C164 requires an 8-bit device address word following a start condition to enable the chip for read or write operations (refer to Figure 1). The most significant bit must be a one followed by the A2, A1 and A0 device select bits (the A1 bit must be the compliment of the A1 input pin signal). The next 3 bits are used for memory block addressing and select one of the eight 256 x 8 memory blocks.
PAGE 10
Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained.
PAGE 11
AT24C164 Figure 1. Device Address Figure 2. Byte Write Figure 3.
PAGE 12
Figure 4. Current Address Read Figure 5. Random Read Figure 6.
PAGE 13
AT24C164 Ordering Information Ordering Code Package AT24C164-10PI-2.7 AT24C164-10SI-2.7 8P3 8S1 Industrial (-40°C to 85°C) AT24C164-10PI-1.8 AT24C164-10SI-1.8 8P3 8S1 Industrial (-40°C to 85°C) Note: Operation Range For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables. Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.
PAGE 14
Packaging Information 8P3 – PDIP E 1 E1 N Top View c eA End View COMMON DIMENSIONS (Unit of Measure = inches) D e D1 A2 A MIN NOM A2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 D 0.355 0.365 0.400 D1 0.005 E 0.300 0.310 0.325 4 E1 0.240 0.250 0.280 3 SYMBOL A b2 b3 b 4 PLCS Side View L Notes: 0.210 0.100 BSC eA 0.300 BSC 0.115 NOTE 2 3 3 e L MAX 0.130 4 0.150 2 1.
PAGE 15
AT24C164 8S1 – JEDEC SOIC 3 2 1 H N Top View e B A D COMMON DIMENSIONS (Unit of Measure = mm) Side View A2 C L SYMBOL MIN NOM MAX A – – 1.75 B – – 0.51 C – – 0.25 D – – 5.00 E – – 4.00 e E End View NOTE 1.27 BSC H – – 6.20 L – – 1.27 Note: This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc. 10/10/01 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 8S1, 8-lead (0.
PAGE 16
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