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Features

• Low-voltage and Standard-voltage Operation

–2.7(V

=2.7Vto5.5V)

–1.8(V

=1.8Vto3.6V)

• Internally Organized 16,384 x 8 and 32,768 x 8

• 2-wire Serial Interface

• Schmitt Trigger, Filtered Inputs for Noise Suppression

• Bidirectional Data Transfer Protocol

• 1 MHz (5V), 400 kHz (2.7V, 2.5V) and 100 kHz (1.8V) Compatibility

• Write Protect Pin for Hardware and Software Data Protection

• 64-byte Page Write Mode (Partial Page Writes Allowed)

• Self-timed Write Cycle (5 ms Typical)

• High Reliability

– Endurance: 100,000 Write Cycles

– Data Retention: 40 Years

• Automotive Grade and Extended Temperature Devices Available

• 8-pin JEDEC PDIP, 8-pin JEDEC and EIAJ SOIC, 8-pin TSSOP, 14-pin TSSOP and 8-ball

dBGA

Packages

Description

The AT24C128/256 provides 131,072/262,144 bits of serial electrically erasable and

programmable read only memory (EEPROM) organized as 16,384/32,768 words of 8

bits each. The device’s cascadable feature allows up to 4 devices to share a common

2-wire bus. The device is optimized for use in many industrial and commercial applica-

tions where low power and low voltage operation are essential. The devices are

available in space-saving 8-pin JEDEC PDIP, 8-pin JEDEC SOIC, 8-pin EIAJ SOIC, 8-

pin TSSOP, 14-pin TSSOP and 8-ball dBGA packages. In addition, the entire family is

available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions.

2-wire Serial

EEPROMs

128K (16,384 x 8)

256K (32,768 x 8)

AT24C128

AT24C256

Rev. 0670H–SEEPR–07/02

Pin Configurations

Pin Name Function

A0 - A1 Address Inputs

SDA Serial Data

SCL Serial Clock Input

WP Write Protect

NC No Connect

8-pin PDIP

GND

VCC

SCL

SDA

8-pin SOIC

GND

VCC

SCL

SDA

14-pin TSSOP

GND

VCC

SCL

SDA

8-ball dBGA

Bottom View

VCC

SCL

SDA

GND

8-pin TSSOP

GND

VCC

SCL

SDA

Summary of content (21 pages)

PAGE 1
Features • Low-voltage and Standard-voltage Operation • • • • • • • • • • • – 2.7 (VCC = 2.7V to 5.5V) – 1.8 (VCC = 1.8V to 3.6V) Internally Organized 16,384 x 8 and 32,768 x 8 2-wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol 1 MHz (5V), 400 kHz (2.7V, 2.5V) and 100 kHz (1.
PAGE 2
Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
PAGE 3
AT24C128/256 Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is opendrain driven and may be wire-ORed with any number of other open-drain or open collector devices.
PAGE 4
Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V. Symbol Test Condition CI/O CIN Note: Max Units Conditions Input/Output Capacitance (SDA) 8 pF VI/O = 0V Input Capacitance (A 0, A1, SCL) 6 pF VIN = 0V 1. This parameter is characterized and is not 100% tested. DC Characteristics(1) Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C, VCC = +1.8V to +5.5V (unless otherwise noted).
PAGE 5
AT24C128/256 AC Characteristics Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 100 pF (unless otherwise noted). Test conditions are listed in Note 2. 1.8-volt Min Max 2.5-volt Min Symbol Parameter fSCL Clock Frequency, SCL tLOW Clock Pulse Width Low 4.7 1.3 0.4 µs tHIGH Clock Pulse Width High 4.0 0.6 0.4 µs tAA Clock Low to Data Out Valid 0.1 tBUF Time the bus must be free before a new transmission can start(1) 4.7 1.3 0.5 µs tHD.
PAGE 6
Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing diagram).
PAGE 7
AT24C128/256 Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O) Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O) SCL SDA 8th BIT ACK WORD n (1) tWR STOP CONDITION Note: START CONDITION 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
PAGE 8
Data Validity Start and Stop Definition Output Acknowledge 8 AT24C128/256 0670H–SEEPR–07/02
PAGE 9
AT24C128/256 Device Addressing The 128K/256K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 1). The device address word consists of a mandatory one, zero sequence for the first five most significant bits as shown. This is common to all 2-wire EEPROM devices. The 128K/256K uses the two device address bits A1, A0 to allow as many as four devices on the same bus.
PAGE 10
Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained.
PAGE 11
AT24C128/256 Figure 3. Page Write Notes: (* = DON’T CARE bit) († = DON’T CARE bit for the 128K) Figure 4. Current Address Read Figure 5. Random Read Notes: (* = DON’T CARE bit) († = DON’T CARE bit for the 128K) Figure 6.
PAGE 12
AT24C128 Ordering Information Ordering Code Package AT24C128-10PI-2.7 AT24C128N-10SI-2.7 AT24C128W-10SI-2.7 AT24C128-10UI-2.7 AT24C128T1-10TI-2.7 8P3 8S1 8S2 8U1 14A2 Industrial (-40°C to 85°C) AT24C128-10PI-1.8 AT24C128N-10SI-1.8 AT24C128W-10SI-1.8 AT24C128-10UI-1.8 AT24C128T1-10TI-1.8 8P3 8S1 8S2 8U1 14A2 Industrial (-40°C to 85°C) Note: Operation Range For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables.
PAGE 13
AT24C128/256 AT24C256 Ordering Information Ordering Code Package AT24C256-10PI-2.7 AT24C256N-10SI-2.7 AT24C256W-10SI-2.7 AT24C256-10UI-2.7 AT24C256-10TI-2.7 8P3 8S1 8S2 8U6 8A2 Industrial (-40°C to 85°C) AT24C256-10PI-1.8 AT24C256N-10SI-1.8 AT24C256W-10SI-1.8 AT24C256-10UI-1.8 AT24C256-10TI-1.8 8P3 8S1 8S2 8U6 8A2 Industrial (-40°C to 85°C) Note: Operation Range For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables.
PAGE 14
Packaging Information 8P3 – PDIP E 1 E1 N Top View c eA End View COMMON DIMENSIONS (Unit of Measure = inches) D e D1 A2 A MIN NOM A2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 D 0.355 0.365 0.400 D1 0.005 E 0.300 0.310 0.325 4 E1 0.240 0.250 0.280 3 SYMBOL A b2 b3 b 4 PLCS Side View L Notes: 0.210 0.100 BSC eA 0.300 BSC 0.115 NOTE 2 3 3 e L MAX 0.130 4 0.150 2 1.
PAGE 15
AT24C128/256 8S1 – JEDEC SOIC 3 2 1 H N Top View e B A D COMMON DIMENSIONS (Unit of Measure = mm) Side View A2 C L SYMBOL MIN NOM MAX A – – 1.75 B – – 0.51 C – – 0.25 D – – 5.00 E – – 4.00 e E End View NOTE 1.27 BSC H – – 6.20 L – – 1.27 Note: This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc. 10/10/01 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 8S1, 8-lead (0.
PAGE 16
8S2 – EIAJ SOIC 1 H N Top View e b A D COMMON DIMENSIONS (Unit of Measure = mm) Side View SYMBOL C A1 L E End View NOM MAX NOTE A 1.78 2.03 A1 0.05 0.33 b 0.35 0.51 5 C 0.18 0.25 5 D 5.13 5.38 E 5.13 5.41 H 7.62 8.38 L 0.51 e Notes: 1. 2. 3. 4. 5. MIN 2, 3 0.89 1.27 BSC 4 This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs aren't included.
PAGE 17
AT24C128/256 8U1 – dBGA E Pin 1 Mark this corner D Top View - Z - 1 7 2 6 3 COMMON DIMENSIONS (Unit of Measure = mm) # 8 Øb . 1 5 M Z 0 . 0 8 M Z X Y # 0 SYMBOL MIN NOM D # d D1 e E1 3.73 D1 0.74 TYP E 4 NOTE 2.21 # 5 MAX Bottom View A2 A A1 Side View E1 0.73 TYP e 0.75 TYP d 0.75 TYP A 0.90 REF A1 0.49 0.52 0.55 A2 0.35 0.38 0.41 Øb 0.47 0.50 0.53 Notes: 1. This drawing is for general information only.
PAGE 18
8U6 – dBGA E Pin 1 Mark this corner D Top View - Z - 7 2 COMMON DIMENSIONS (Unit of Measure = mm) Øb 0 . 1 5 M Z 0 . 0 8 M Z X Y # 1 # 8 SYMBOL MIN − D 3 # 6 d D1 e E1 − 3.73 A2 A A1 Bottom View Side View − − 2.25 E1 0.75 TYP e 0.75 TYP d 0.75 TYP A 0.90 REF A1 0.49 0.52 0.55 A2 0.35 0.38 0.41 Øb 0.47 0.50 0.53 Notes: 1. This drawing is for general information only. No JEDEC drawing to refer to for additional information. 2.
PAGE 19
AT24C128/256 8A2 – TSSOP 3 2 1 Pin 1 indicator this corner E1 E L1 N L Top View End View COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A b D MIN NOM MAX NOTE 2.90 3.00 3.10 2, 5 3, 5 E e D A2 6.40 BSC E1 4.30 4.40 4.50 A – – 1.20 A2 0.80 1.00 1.05 b 0.19 – 0.30 e Side View L 0.65 BSC 0.45 L1 Notes: 4 0.60 0.75 1.00 REF 1. This drawing is for general information only.
PAGE 20
14A2 – TSSOP b L L1 E1 E End View e COMMON DIMENSIONS (Unit of Measure = mm) Top View SYMBOL D D A MIN 4.90 E A2 E1 NOM MAX 5.00 5.10 2, 5 4.50 3, 5 6.40 BSC 4.30 4.40 A 1.20 A2 0.80 b 0.19 e Side View L L1 Notes: R 20 1.00 TITLE 14A2,14-lead (4.4 x 5 mm Body), 0.65 Pitch, Thin Shrink Small Outline Package (TSSOP) 1.05 0.30 4 0.65 BSC 0.45 0.60 0.75 1.00 REF 1. This drawing is for general information only.
PAGE 21
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