Manual

7
AT24C1024B [Preliminary]
5194D–SEEPR–5/07
Figure 3. Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)
Note: 1. The write cycle time t
WR
is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
Figure 4. Data Validity
Figure 5. Start and Stop Definition
t
wr
(1)
STOP
CONDITION
START
CONDITION
WORDn
ACK
8th BIT
S
CL
S
DA