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Features

• EE Programmable 65,536 x 1-, 131,072 x 1-, 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-,

2,097,152 x 1-, and 4,194,304 x 1-bit Serial Memories Designed to Store Configuration

Programs for Field Programmable Gate Arrays (FPGAs)

• Available as a 3.3V (±10%) and 5.0V (±5% Commercial, ±10% Industrial) Version

• In-System Programmable (ISP) via Two-Wire Bus

• Simple Interface to SRAM FPGAs

•

Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera FLEX

, APEX

™

Devices,

Lucent ORCA

FPGAs, Xilinx XC3000

™

, XC4000

™

, XC5200

™

, Spartan

, Virtex

FPGAs

• Cascadable Read-back to Support Additional Configurations or Higher-density Arrays

• Very Low-power CMOS EEPROM Process

• Programmable Reset Polarity

• Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC

Packages), 8-lead PDIP, 8-lead SOIC, 20-lead PLCC, 20-lead SOIC, 44-lead PLCC and

44-lead TQFP Packages

• Emulation of Atmel’s AT24CXXX Serial EEPROMs

• Low-power Standby Mode

• High-reliability

– Endurance: 100,000 Write Cycles

– Data Retention: 90 Years for Industrial Parts (at 85°C) and 190 Years for

Commercial Parts (at 70°C)

Description

The AT17LV series FPGA Configuration EEPROMs (Configurators) provide an easy-

to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The

AT17LV series device is packaged in the 8-lead LAP, 8-lead PDIP, 8-lead SOIC, 20-

lead PLCC, 20-lead SOIC, 44-lead PLCC and 44-lead TQFP, see Table 1. The

AT17LV series Configurators uses a simple serial-access procedure to configure one

or more FPGA devices. The user can select the polarity of the reset function by pro-

gramming four EEPROM bytes. These devices also support a write-protection

mechanism within its programming mode.

The AT17LV series configurators can be programmed with industry-standard program-

mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.

Notes: 1. The 8-lead LAP package has the same footprint as the 8-lead SOIC. Since an 8-

lead SOIC package is not available for the AT17LV512/010/002 devices, it is possi-

ble to use an 8-lead LAP package instead.

2. The pinout for the AT17LV65/128/256 devices is not pin-for-pin compatible with the

AT17LV512/010/002 devices.

3. Refer to the AT17Fxxx datasheet, available on the Atmel web site.

Table 1. AT17LV Series Packages

Package

AT17LV65/

AT17LV128/

AT17LV256

AT17LV512/

AT17LV010 AT17LV002 AT17LV040

8-lead LAP Yes Yes Yes

(3)

8-lead PDIP Yes Yes – –

8-lead SOIC Yes

Use 8-lead LAP

(1)

Use 8-lead LAP

(1)

(3)

20-lead PLCC Yes Yes Yes –

20-lead SOIC Yes

(2)

Ye s

(2)

Ye s

(2)

–

44-lead PLCC – – Yes Yes

44-lead TQFP – – Yes Yes

FPGA

Configuration

EEPROM

Memory

AT17LV65

AT17LV128

AT17LV256

AT17LV512

AT17LV010

AT17LV002

AT17LV040

3.3V and 5V

System Support

Rev. 2321D–CNFG–10/02

Summary of content (24 pages)

PAGE 1
Features • EE Programmable 65,536 x 1-, 131,072 x 1-, 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-, • • • • • • • • • • • 2,097,152 x 1-, and 4,194,304 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs) Available as a 3.3V (±10%) and 5.
PAGE 2
Pin Configuration 8-lead LAP DATA CLK (1) (WP ) RESET/OE CE 1 2 3 4 VCC SER_EN CEO (A2) GND 8 7 6 5 8-lead SOIC DATA CLK (1) (WP ) RESET/OE CE 1 2 3 4 VCC SER_EN CEO (A2) GND 8 7 6 5 8-lead PDIP DATA CLK (1) (WP ) RESET/OE CE 1 2 3 4 VCC SER_EN CEO (A2) GND 8 7 6 5 18 17 16 15 14 9 10 11 12 13 4 5 6 7 8 NC SER_EN NC NC (READY(2)) CEO (A2) NC GND NC NC NC CLK (WP1(2)) NC (WP(1)) RESET/OE (WP2(2)) NC CE 3 2 1 20 19 NC DATA NC VCC NC 20-lead PLCC Notes: 2 1.
PAGE 3
AT17LV65/128/256/512/010/002/040 20-lead SOIC(1) NC DATA NC CLK NC RESET/OE NC CE NC GND Note: 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC NC NC SER_EN NC NC CEO (A2) NC NC NC 1. This pinout only applies to AT17LV65/128/256 devices. 20-lead SOIC(1) DATA NC CLK NC NC NC NC RESET/OE NC CE Note: 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC NC SER_EN NC NC NC NC CEO NC GND 1. This pinout only applies to AT17LV512/010/002 devices.
PAGE 4
6 5 4 3 2 1 44 43 42 41 40 NC CLK NC NC DATA NC VCC NC NC SER_EN NC 44 PLCC (WP1(1)) NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC READY 39 38 37 36 35 34 33 32 31 30 29 NC RESET/OE NC CE NC NC GND NC NC CEO/A2 NC 18 19 20 21 22 23 24 25 26 27 28 7 8 9 10 11 12 13 14 15 16 17 44 43 42 41 40 39 38 37 36 35 34 NC CLK NC NC DATA NC VCC NC NC SER_EN NC 44 TQFP 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 NC NC NC NC NC NC NC NC NC NC READY NC RESET/OE NC CE NC NC GND
PAGE 5
AT17LV65/128/256/512/010/002/040 Block Diagram SER_EN WP1(2) WP2(2) POWER ON RESET (2) READY Notes: Device Description (1) 1. This pin is only available on AT17LV65/128/256 devices. 2. This pin is only available on AT17LV512/010/002 devices. The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) interface directly with the FPGA device control signals.
PAGE 6
Pin Description AT17LV65/ AT17LV128/ AT17LV256 8 DIP/ LAP/ SOIC 20 PLCC AT17LV512/ AT17LV010 20 SOIC 8 DIP/ LAP 20 PLCC AT17LV002 AT17LV040 20 SOIC 8 DIP/ LAP/ SOIC 20 PLCC 20 SOIC 44 PLCC 44 TQFP 44 PLCC 44 TQFP Name I/O DATA I/ O 1 2 2 1 2 1 1 2 1 2 40 2 40 CLK I 2 4 4 2 4 3 2 4 3 5 43 5 43 WP1 I – – – – 5 – – 5 – – – – – RESET/OE I 3 6 6 3 6 8 3 6 8 19 13 19 13 WP2 I – 7 – – 7 – – – – – CE I GND CEO 4 8 8 4 8
PAGE 7
AT17LV65/128/256/512/010/002/040 CE Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the address counter and enables the data output driver. A High level on CE disables both the address and bit counters and forces the device into a low-power standby mode. Note that this pin will not enable/disable the device in the Two-Wire Serial Programming mode (SER_EN Low). GND Ground pin. A 0.2 µF decoupling capacitor between VCC and GND is recommended.
PAGE 8
FPGA Master Serial Mode Summary The I/O and logic functions of any SRAM-based FPGA are established by a configuration program. The program is loaded either automatically upon power-up, or on command, depending on the state of the FPGA mode pins. In Master mode, the FPGA automatically loads the configuration program from an external memory. The AT17LV Serial Configuration EEPROM has been designed for compatibility with the Master Serial mode.
PAGE 9
AT17LV65/128/256/512/010/002/040 Absolute Maximum Ratings* Operating Temperature.................................... -40°C to +85°C *NOTICE: Storage Temperature ..................................... -65 °C to +150°C Voltage on Any Pin with Respect to Ground ..............................-0.1V to VCC +0.5V Supply Voltage (VCC) .........................................-0.5V to +7.0V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
PAGE 10
DC Characteristics VCC = 3.3V ± 10% AT17LV65/ AT17LV128/ AT17LV256 Symbol Description VIH AT17LV512/ AT17LV010 AT17LV002/ AT17LV040 Min Max Min Max Min Max Units High-level Input Voltage 2.0 VCC 2.0 VCC 2.0 VCC V VIL Low-level Input Voltage 0 0.8 0 0.8 0 0.8 V VOH High-level Output Voltage (IOH = -2.
PAGE 11
AT17LV65/128/256/512/010/002/040 AC Characteristics CE TSCE TSCE THCE RESET/OE TLC THOE THC CLK TOE TOH TCAC TDF TCE DATA TOH AC Characteristics when Cascading RESET/OE CE CLK TCDF DATA FIRST BIT LAST BIT TOCK TOCE TOOE CEO TOCE 11 2321D–CNFG–10/02
PAGE 12
AC Characteristics VCC = 3.
PAGE 13
AT17LV65/128/256/512/010/002/040 AC Characteristics VCC = 5V ± 5% Commercial; VCC = 5V ± 10% Industrial AT17LV65/128/256 Commercial Symbol Description Min Max AT17LV512/010/002/040 Industrial Min Max Units 30 35 ns 45 45 45 ns 55 50 50 ns TOE OE to Data Delay 30 35 TCE (1) CE to Data Delay 45 CLK to Data Delay 50 TCAC Data Hold from CE, OE, or CLK TOH TDF (2) 0 CE or OE to Data Float Delay 0 50 Min Max Industrial Max (1) (1) Commercial 0 Min 0 50 ns 50 50 ns
PAGE 14
Thermal Resistance Coefficients(1) Package Type 8CN4 8P3 8S1 20J 20S2 44A 44J Notes: 14 Leadless Array Package (LAP) Plastic Dual Inline Package (PDIP) Plastic Gull Wing Small Outline (SOIC) Plastic Leaded Chip Carrier (PLCC) Plastic Gull Wing Small Outline (SOIC) Thin Plastic Quad Flat Package (TQFP) Plastic Leaded Chip Carrier (PLCC) qJC [°C/W] qJA [°C/W] (2) qJC [°C/W] qJA [°C/W] (2) qJC [°C/W] qJA [°C/W] (2) qJC [°C/W] qJA [°C/W] (2) AT17LV65/ AT17LV128/ AT17LV256 AT17LV512/ AT17LV01
PAGE 15
AT17LV65/128/256/512/010/002/040 Figure 1. Ordering Code AT17LV65A-10PC Voltage Size (Bits) Special Pinouts Package Temperature 3.0V to 5.
PAGE 16
Ordering Information Memory Size 64-Kbit(1) 128-Kbit(1) 256-Kbit(1) 512-Kbit(1) 1-Mbit(1) 2-Mbit(1) 4-Mbit(1) Note: 16 Package Operation Range AT17LV65-10CC AT17LV65-10PC AT17LV65-10NC AT17LV65-10JC AT17LV65-10SC Ordering Code 8CN4 8P3 8S1 20J 20S2 Commercial (0°C to 70°C) AT17LV65-10CI AT17LV65-10PI AT17LV65-10NI AT17LV65-10JI AT17LV65-10SI 8CN4 8P3 8S1 20J 20S2 Industrial (-40°C to 85°C) AT17LV128-10CC AT17LV128-10PC AT17LV128-10NC AT17LV128-10JC AT17LV128-10SC 8CN4 8P3 8S1 20J 20S2 Co
PAGE 17
AT17LV65/128/256/512/010/002/040 Packaging Information 8CN4 – LAP Marked Pin1 Indentifier E A A1 D Top View Side View Pin1 Corner L1 0.10 mm TYP 8 1 e COMMON DIMENSIONS (Unit of Measure = mm) 2 7 3 6 b 5 4 e1 L Bottom View SYMBOL MIN NOM MAX A 0.94 1.04 1.14 A1 0.30 0.34 0.38 b 0.45 0.50 0.55 D 5.89 5.99 6.09 E 4.89 5.99 6.09 e 1.27 BSC e1 1.10 REF NOTE 1 L 0.95 1.00 1.05 1 L1 1.25 1.30 1.35 1 Note: 1. Metal Pad Dimensions.
PAGE 18
8P3 – PDIP E 1 E1 N Top View c eA End View COMMON DIMENSIONS (Unit of Measure = inches) D e D1 A2 A MIN NOM A2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 D 0.355 0.365 0.400 D1 0.005 E 0.300 0.310 0.325 4 E1 0.240 0.250 0.280 3 SYMBOL A b2 L b3 b 4 PLCS Side View Notes: NOTE 0.210 0.100 BSC eA 0.300 BSC 0.115 2 3 3 e L MAX 0.130 4 0.150 2 1.
PAGE 19
AT17LV65/128/256/512/010/002/040 8S1 – SOIC 3 2 1 H N Top View e B A D COMMON DIMENSIONS (Unit of Measure = mm) Side View A2 C L SYMBOL MIN NOM MAX A – – 1.75 B – – 0.51 C – – 0.25 D – – 5.00 E – – 4.00 e E End View NOTE 1.27 BSC H – – 6.20 L – – 1.27 Note: This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc. 10/10/01 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 8S1, 8-lead (0.
PAGE 20
J – PLCC PIN NO. 1 1.14(0.045) X 45˚ 1.14(0.045) X 45˚ 0.318(0.0125) 0.191(0.0075) IDENTIFIER e E1 E D2/E2 B1 B A2 D1 A1 D A 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side.
PAGE 21
AT17LV65/128/256/512/010/002/040 20S2 – SOIC C 1 L E H N A1 Top View End View COMMON DIMENSIONS (Unit of Measure = inches) e SYMBOL b A A D Side View MIN NOM 0.0926 MAX NOTE 0.1043 A1 0.0040 0.0118 b 0.0130 0.0200 C 0.0091 0.0125 D 0.4961 0.5118 1 E 0.2914 0.2992 2 H 0.3940 0.4190 L 0.0160 0.050 e 4 3 0.050 BSC Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-013, Variation AC for additional information. 2.
PAGE 22
44A – TQFP PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. A2 0.95 1.00 1.05 D 11.75 12.
PAGE 23
AT17LV65/128/256/512/010/002/040 44J – PLCC 1.14(0.045) X 45˚ PIN NO. 1 1.14(0.045) X 45˚ 0.318(0.0125) 0.191(0.0075) IDENTIFIER E1 D2/E2 B1 E B e A2 D1 A1 D A 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side.
PAGE 24
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