Instruction Manual

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Features

• Programmable 4,194,304 x 1 and 8,388,608 x 1-bit Serial Memories Designed to Store

Configuration Programs for Field Programmable Gate Arrays (FPGAs)

• 3.3V Output Capability

• 5V Tolerant I/O Pins

• In-System Programmable (ISP) via 2-wire Bus

• Simple Interface to SRAM FPGAs

• Compatible with Atmel AT40K and AT94K Devices, Altera FLEX

, APEX

™

Devices,

Lucent ORCA

FPGAs, Xilinx XC3000

™

, XC4000

™

, XC5200

™

, Spartan

, Virtex

FPGAs,

Motorola MPA1000 FPGAs

• Cascadable Read-back to Support Additional Configurations or Higher-density Arrays

• Low-power CMOS FLASH Process

• Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC

Packages), 20-lead PLCC, 44-lead PLCC and 44-lead TQFP Packages

• Emulation of Atmel’s AT24CXXX Serial EEPROMs

• Low-power Standby Mode

• Single Device Capable of Holding 4 Bit Stream Files Allowing Simple System

Reconfiguration

• Fast Serial Download Speeds up to 33 MHz

Description

The AT17F Series of In-System Programmable Configuration PROMs (Configurators)

provide an easy-to-use, cost-effective configuration memory for Field Programmable

Gate Arrays. The AT17F Series device is packaged in the 8-lead LAP, 20-lead PLCC,

44-lead PLCC and 44-lead TQFP, see Table 1. The AT17F Series Configurator uses a

simple serial-access procedure to configure one or more FPGA devices.

The AT17F Series Configurators can be programmed with industry-standard program-

mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.

Table 1. AT17F Series Packages

Package AT17F040 AT17F080

8-lead LAP Yes Yes

20-lead PLCC Yes Yes

44-lead PLCC – Yes

44-lead TQFP – Yes

In-System

Programmable

Configuration

PROM

AT17F040

AT17F080

Advance

Information

Rev. 3039C–CNFG–11/02

Summary of content (18 pages)

PAGE 1
Features • Programmable 4,194,304 x 1 and 8,388,608 x 1-bit Serial Memories Designed to Store • • • • • • • • • • • • Configuration Programs for Field Programmable Gate Arrays (FPGAs) 3.
PAGE 2
Pin Configuration 8-lead LAP DATA CLK RESET/OE CE 1 2 3 4 8 7 6 5 VCC SER_EN CEO (A2) GND 18 17 16 15 14 9 10 11 12 13 4 5 6 7 8 NC SER_EN PAGE_EN READY CEO (A2) NC GND PAGESEL0 NC NC CLK NC RESET/OE PAGESEL1 CE 3 2 1 20 19 NC DATA NC VCC NC 20-lead PLCC 2 AT17F040/080 3039C–CNFG–11/02
PAGE 3
NC RESET/OE PAGESEL0 CE NC NC GND PAGESEL1 NC CEO(A2) NC 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 NC CLK NC NC DATA PAGE_EN VCC NC NC SER_EN NC NC RESET/OE PAGESEL0 CE NC NC GND PAGESEL1 NC CEO/A2 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC 3039C–CNFG–11/02 6 5 4 3 2 1 44 43 42 41 40 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NC CLK NC NC DATA PAGE_EN VCC NC NC SER_EN NC AT17F040/080 44 PLCC 39 38 37 36 35 34 33 32 31 30 29 1
PAGE 4
Block Diagram READY PAGE_EN PAGESEL0 PAGESEL1 Power-on Reset Reset Clock/Oscillator Logic CEO(A2) Config. Page Select Serial Download Logic 2-wire Serial Programming Flash Memory CLK CE/WE/OE Data Address DATA CE Control Logic RESET/OE SER_EN Device Description The control signals for the configuration memory device (CE, RESET/OE and CLK) interface directly with the FPGA device control signals.
PAGE 5
AT17F040/080 Pin Description AT17F040 AT17F080 Name I/O 8 LAP 20 PLCC 8 LAP 20 PLCC 44 PLCC 44 TQFP DATA I/O 1 2 1 2 2 40 CLK I 2 4 2 4 5 43 PAGE_EN I – 16 – 16 1 39 PAGESEL0 I – 11 – 5 20 14 PAGESEL1 I – 7 – 7 25 19 RESET/OE I 3 6 3 6 19 13 CE I 4 8 4 8 21 15 GND – 5 10 5 10 24 18 CEO O 6 14 6 14 27 21 A2 I READY O – 15 – 15 29 23 SER_EN I 7 17 7 17 41 35 VCC – 8 20 8 20 44 38 DATA Three-state DATA o
PAGE 6
RESET/OE Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low level on RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the data output driver. CE Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the address counter and enables the data output driver. A High level on CE disables both the address and bit counters and forces the device into a low-power standby mode.
PAGE 7
AT17F040/080 FPGA Master Serial Mode Summary The I/O and logic functions of any SRAM-based FPGA are established by a configuration program. The program is loaded either automatically upon power-up, or on command, depending on the state of the FPGA mode pins. In Master mode, the FPGA automatically loads the configuration program from an external memory. The AT17F Serial Configuration PROM has been designed for compatibility with the Master Serial mode.
PAGE 8
Absolute Maximum Ratings* Operating Temperature...................................... -4°C to +85°C *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. Storage Temperature .......
PAGE 9
AT17F040/080 AC Characteristics CE TSCE TSCE THCE RESET/OE TLC THOE THC CLK TOE TOH TCAC TDF TCE DATA TOH AC Characteristics when Cascading RESET/OE CE CLK TCDF DATA FIRST BIT LAST BIT TOCK TOCE TOOE CEO TOCE 9 3039C–CNFG–11/02
PAGE 10
AC Characteristics AT17F040 Symbol Description TOE(1) OE to Data Delay TCE(1) CE to Data Delay TCAC(1) CLK to Data Delay TOH Data Hold from CE, OE, or CLK TDF(2) CE or OE to Data Float Delay TLC CLK Low Time THC CLK High Time TSCE Min AT17F080 Max Min Max Units Commercial 50 50 ns Industrial 55 55 ns Commercial 60 55 ns Industrial 60 60 ns Commercial 75 55 ns Industrial 80 60 ns Commercial 0 0 ns Industrial 0 0 ns Commercial 55 50 ns Industrial 55
PAGE 11
AT17F040/080 AC Characteristics When Cascading AT17F040 Symbol Description TCDF(2) CLK to Data Float Delay TOCK(1) CLK to CEO Delay TOCE(1) CE to CEO Delay TOOE(1) RESET/OE to CEO Delay FMAX Maximum Input Clock Frequency Notes: Min AT17F080 Max Min Max Units Commercial 60 50 ns Industrial 60 50 ns Commercial 55 50 ns Industrial 60 55 ns Commercial 55 35 ns Industrial 60 40 ns Commercial 40 35 ns Industrial 45 35 ns Commercial 33 33 MHz Industrial 33 3
PAGE 12
Thermal Resistance Coefficients(1) Package Type 8CN4 20J 44A 44J Notes: 12 Leadless Array Package (LAP) Plastic Leaded Chip Carrier (PLCC) Thin Plastic Quad Flat Package (TQFP) Plastic Leaded Chip Carrier (PLCC) AT17F040 qJC [°C/W] qJA [°C/W] AT17F080 – (2) – qJC [°C/W] – qJA [°C/W](2) – qJC [°C/W] – 17 – 62 qJC [°C/W] – 15 qJA [°C/W](2) – 50 qJA [°C/W] (2) 1.
PAGE 13
AT17F040/080 Ordering Information Memory Size 4-Mbit 8-Mbit Ordering Code Package Operation Range AT17F040-30CC AT17F040-30BJC 8CN4 - 8 LAP 20J - 20 PLCC Commercial (0°C to 70°C) AT17F040-30CI AT17F040-30BJI 8CN4 - 8 LAP 20J - 20 PLCC Industrial (-40°C to 85°C) AT17F080-30CC AT17F080-30JC AT17F080-30TQC AT17F080-30BJC 8CN4 - 8 LAP 20J - 20 PLCC 44A - 44 TQFP 44J - 44 PLCC Commercial (0°C to 70°C) AT17F080-30CI AT17F080-30JI AT17F080-30TQI AT17F080-30BJI 8CN4 - 8 LAP 20J - 20 PLCC 44A - 44 TQF
PAGE 14
Packaging Information 8CN4 – LAP Marked Pin1 Indentifier E A A1 D Top View Side View Pin1 Corner L1 0.10 mm TYP 8 1 e COMMON DIMENSIONS (Unit of Measure = mm) 2 7 3 6 b 5 4 e1 L Bottom View SYMBOL MIN NOM MAX A 0.94 1.04 1.14 A1 0.30 0.34 0.38 b 0.45 0.50 0.55 D 5.89 5.99 6.09 E 4.89 5.99 6.09 e NOTE 1 1.27 BSC e1 1.10 REF L 0.95 1.00 1.05 1 L1 1.25 1.30 1.35 1 Note: 1. Metal Pad Dimensions.
PAGE 15
AT17F040/080 20J – PLCC PIN NO. 1 1.14(0.045) X 45˚ 1.14(0.045) X 45˚ 0.318(0.0125) 0.191(0.0075) IDENTIFIER e E1 E D2/E2 B1 B A2 D1 A1 D A 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side.
PAGE 16
44A – TQFP PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 11.75 12.
PAGE 17
AT17F040/080 44J – PLCC 1.14(0.045) X 45˚ PIN NO. 1 1.14(0.045) X 45˚ 0.318(0.0125) 0.191(0.0075) IDENTIFIER E1 D2/E2 B1 E B e A2 D1 A1 D A 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side.
PAGE 18
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