Owner's manual

Preliminary
APR6016 Data Sheet
Page 2 Voice Recording & Playback Device
Revision 1.0
Functional Description
The EXTCLK pin allows the use of an external samplin
g
clock. This input can accept a wide ran
g
e of fre
q
uencies
dependin
g
on the divider ratio pro
g
rammed into the divider
that follows the clock. Alternativel
y
, the pro
g
rammable inter-
nal oscillator can be used to suppl
y
the samplin
g
clock. The
Mux followin
g
both si
g
nals automaticall
y
selects the EXTCLK
si
g
nal if a clock is present, otherwise the internal oscillator
source is chosen. Detailed information on how to pro
g
ram the
divider and internal oscillator can be found in the explanation
of the
PWRUP
command, which appears in the
OpCode
Command Description
section. Guidance on how to choose
the appropriate sample clock fre
q
uenc
y
can be found in the
Sampling Rate & Voice Quality
section.
The audio si
g
nal containin
g
the content
y
ou wish to record
should be fed into the differential inputs ANAIN-, and
ANAIN+. After pre-amplification the si
g
nal is routed into the
anti-aliasin
g
filter. The anti-aliasin
g
filter automaticall
y
adapts
its response based on the sample rate bein
g
used. No exter-
nal anti-aliasin
g
filter is therefore re
q
uired.
After passin
g
throu
g
h the anti-alias filter, the si
g
nal is fed into
the sample and hold circuit which works in con
j
unction with
the Analo
g
Write Circuit to store each analo
g
sample in a
flash memor
y
cell.
When a read operation is desired the Analo
g
Read Circuit
extracts the analo
g
data from the memor
y
arra
y
and feeds
the si
g
nal to the Internal Low Pass Filter. The low pass filter
converts the individual samples into a continuous output. The
output si
g
nal then
g
oes to the s
q
uelch control circuit and dif-
ferential output driver. The differential output driver feeds the
ANAOUT+ and ANAOUT- pins. Both differential output pins
swin
g
around a 1.23V potential.
The s
q
uelch control circuit automaticall
y
reduces the output
si
g
nal b
y
6 dB durin
g
q
uiet passa
g
es. A cop
y
of the s
q
uelch
control si
g
nal is present on the /SQLOUT pin to facilitate
reducin
g
g
ain in the external amplifier as well. For more infor-
mation, refer to the
Squelch
section.
After passin
g
throu
g
h the s
q
uelch circuit the output si
g
nal
g
oes to the output amplifier. The output amplifier drives a sin-
g
le ended output on the AUDOUT pin. The sin
g
le ended out-
put swin
g
s around a 1.23V potential.
All SPI control and hand shakin
g
si
g
nals are routed to the
Master Control Circuit. This circuit decodes all the SPI si
g
nals
and
g
enerates all the internal control si
g
nals. It also contains
the status re
g
ister used for examinin
g
the current status of
the APR6016.
Figure 2 APR6016 Block Diagram
SAC
Low Pass
Master Control Circuit
Amp
SCLK
/CS
DI
DO
/INT
/RESET
AUDOUT
/SQLOUT
Squelch
Amp
ANAOUT+
ANAOUT-
/BUSY
SQLCAP
Row Decoder
Column Decoder
Column Address
Row
Address
Single Analog
Memory Cell
3.84 Mcell Memory Array
Write Circuit
Low Pass
Read Circuit
Analog input/output
to Memory array
Pre-
Amp
ANAIN+
ANAIN-
Programmable Internal
Oscillator
Mux
EXTCLK
Programmable
Divider