User Manual

APLUS INTEGRATED CIRCUITS INC. APC5830
www.aplusinc.com.tw TEL : [phone]
9
z 3FF4 : BANK REGISTER FOR CPU. WRITE ONLY.
z 3FF5 : BANK REGISTER MSB BIT FOR CPU. WRITE ONLY.
BANK REGISTER IS 9 BITS REGISTER($3FF5 BIT0, $3FF4 BIT7-0).
THE MEMORY RANGE OF BANK IS FROM $4000 TO $7FFF.
BIT 1: RESERVED.
BIT 2: = 1 VOICE0 BUFFER BE TRANSFERRED TO DAC PORT DIRECTLY.(DEFAULT)
= 0 VOICE0 BUFFER WILL BE TRANSFERRED TO DAC PORT WHEN TIMER_B NMI HAPPEN.
BIT 7-3 : RESERVED.
z 3FF6 : PORT_C[7..0] DATA REGISTER. READ AND WRITE.
z 3FF7 : PORT_C[15..8] DATA REGISTER. READ AND WRITE.
z 3FF8: PORT_C[7..0] DIRECTION REGISTER. WRITE ONLY.
AN ‘1’ IN THIS REGISTER WILL SET THE CORRESPONDING PIN OF PORT_C TO BE OUTPUT.
THE DEFAULT VALUE FOR EACH BIT IS ZERO.
z 3FF9: PORT_C[15..8] DIRECTION REGISTER. WRITE ONLY.
AN ‘1’ IN THIS REGISTER WILL SET THE CORRESPONDING PIN OF PORT_C TO BE OUTPUT.
THE DEFAULT VALUE FOR EACH BIT IS ZERO.
z 3FFA :ADC REGISTER. READ ONLY.
WHEN THE TIMER B NMI OCCURS, THE A/D CONVERSION PROCESS STARTS AND THE S/H
CIRCUIT STOP SAMPLING AND BEGIN HOLDING IT UNTIL THE ADC PROCESS IS FINISHED.
THE ADC INT WILL GENERATE WHEN ADC PROCESS IS FINISHED.
z 3FFB,3FFC :….NO USE
z 3FFD : ……NO USE
z 3FFE: VOICE CHANNEL 1 LOW BYTE AND SYSTEM CONTROL 3. WRITE ONLY.
3FFE
0 1
BIT - 0
SEPARATE MODE FOR DAC
OUTPUT
(DEFAULT)
MIX MODE FOR DAC OUTPUT.
BIT - 1
SEPARATE MODE FOR PWM
OUTPUT
(DEFAULT)
MIX MODE FOR PWM OUTPUT
BIT - 2 NO USE(MUST 0)
BIT - 3 NO USE (MUST 0)
BIT – 7 ~ 4 VOICE CHANNEL 1 LOW NIBBLE BYTE.