User Manual

APLUS INTEGRATED CIRCUITS INC. APC5830
www.aplusinc.com.tw TEL : [phone]
7
z 3FE2 System control 2. Write only.
3FE2
0 1
BIT - 0
=1 Æ ENTRY STAND-BY MODE. IN STAND-BY MODE, HOLD CPU
.
THE NMI AND IRQ WILL WAKE UP THE CPU.
BIT - 1
=1 Æ ENTRY SLEEP MODE. IN SLEEP MODE , THE BOTH OF MAIN
SYSTEM CLOCK AND
32768HZ WILL BESTOPPED, SO ALL
FUNCTION ARE STOPPED AND ONLY EXTERNAL INTERRUP
T
CAN WAKE UP THIS CHIP
BIT – 3 ~ 2
00 : SYSTEM CLOCK = FXOSC/2 X 256(4.19MHZ)(DEFAULT).
01 : SYSTEM CLOCK = FXOSC/2 X 512(8.38MHZ)
10 : SYSTEM CLOCK = FXOSC/2 X 768(12.58MHZ)
BIT- 7 ~ 4
0XXX : FIX-TIMER DISABLE.
1000 : FIX-TIMER = 64HZ.
1001 : FIX-TIMER = 32HZ.
1010 : FIX-TIMER = 16HZ.
1011 : FIX-TIMER = 8HZ.
1100 : FIX-TIMER = 4HZ.
1101 : FIX-TIMER = 2HZ.
1110 : FIX-TIMER = 1HZ.
1111 : FIX-TIMER = 0.5HZ
z 3FE3 : PORT_A[7..0] INTERRUPT ENABLE REGISTER. WRITE ONLY.
AN ‘0’ IN THIS REGISTER WILL SET THE INTERRUPT FUNCTION OF THE CORRESPONDING PIN
OF
PORT_A TO BE ENABLED. THE DEFAULT VALUE FOR EACH BIT IS ‘1’.
z 3FE4 : PORT_A[7..0] DATA REGISTER. READ AND WRITE.
z 3FE5 : PORT_A[7..0] DIRECTION REGISTER. WRITE ONLY.
AN ‘1’ IN THIS REGISTER WILL SET THE CORRESPONDING PIN OF PORT_A TO BE OUTPUT.
THE DEFAULT VALUE FOR EACH BIT IS ZERO.
z 3FE6: PORT_B[7..0] DATA REGISTER. WRITE ONLY.
z 3FE7 : CLEAR WATCHDOG TIMER. WRITE ONLY.
THE WATCHDOG TIMER RESET WILL HAPPEN IF THE PROGRAMMER DO NOT CLEAR THE
WATCHDOG TIMER BEFORE WATCHDOG TIMER TIME-OUT.