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ADC12L063

12-Bit, 62 MSPS, 354 mW A/D Converter with Internal

Sample-and-Hold

General Description

The ADC12L063 is a monolithic CMOS analog-to-digital con-

verter capable of converting analog input signals into 12-bit

digital words at 62 Megasamples per second (MSPS), mini-

mum. This converter uses a differential, pipelined architec-

ture with digital error correction and an on-chip sample-and-

hold circuit to minimize die size and power consumption

while providing excellent dynamic performance. Operating

on a single 3.3V power supply, this device consumes just

354 mW at 62 MSPS, including the reference current. The

Power Down feature reduces power consumption to just 50

mW.

The differential inputs provide a full scale input swing equal

REF

with the possibility of a single-ended input. Full use

of the differential input is recommended for optimum perfor-

mance. For ease of use, the buffered, high impedance,

single-ended reference input is converted on-chip to a differ-

ential reference for use by the processing circuitry. Output

data format is 12-bit offset binary.

This device is available in the 32-lead LQFP package and

will operate over the industrial temperature range of −40˚C to

+85˚C.

Features

n Single supply operation

n Low power consumption

n Power down mode

n On-chip reference buffer

Key Specifications

n Resolution 12 Bits

n Conversion Rate 62 MSPS(min)

n Bandwidth 170MHz

n DNL

0.5 LSB(typ)

n INL

1.0 LSB(typ)

n SNR 66 dB(typ)

n SFDR 78 dB(typ)

n Data Latency 6 Clock Cycles

n Supply Voltage +3.3V

300 mV

n Power Consumption, 62 MHz 354 mW(typ)

Applications

n Ultrasound and Imaging

n Instrumentation

n Cellular Base Stations/Communications Receivers

n Sonar/Radar

n xDSL

n Wireless Local Loops

n Data Acquisition Systems

n DSP Front Ends

Connection Diagram

20026301

November 2002

ADC12L063 12-Bit, 62 MSPS, 354 mW A/D Converter with Internal Sample-and-Hold

Summary of content (22 pages)

PAGE 1
ADC12L063 12-Bit, 62 MSPS, 354 mW A/D Converter with Internal Sample-and-Hold General Description Features The ADC12L063 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at 62 Megasamples per second (MSPS), minimum. This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-andhold circuit to minimize die size and power consumption while providing excellent dynamic performance.
PAGE 2
ADC12L063 Ordering Information Industrial (−40˚C ≤ TA ≤ +85˚C) Package ADC12L063CIVY 32 Pin LQFP ADC12L063CIVYX 32 Pin LQFP Tape and Reel ADC12L063EVAL Evaluation Board Block Diagram 20026302 www.national.
PAGE 3
ADC12L063 Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit Description ANALOG I/O VIN+ Non-Inverting analog signal Input. With a 1.0V reference voltage the input signal level is 1.0 VP-P. 3 VIN− Inverting analog signal Input. With a 1.0V reference voltage the input signal level is 1.0 VP-P. This pin may be connected to VCM for single-ended operation, but a differential input signal is required for best performance. 1 VREF Reference input.
PAGE 4
ADC12L063 Pin Descriptions and Equivalent Circuits Pin No. Symbol 14–19, 22–27 D0–D11 Equivalent Circuit (Continued) Description Digital data output pins that make up the 12-bit conversion results. D0 is the LSB, while D11 is the MSB of the offset binary output word. ANALOG POWER 5, 6, 29 VA 4, 7, 28 AGND Positive analog supply pins. These pins should be connected to a quiet +3.3V source and bypassed to AGND with 0.
PAGE 5
Soldering Temperature, Infrared, 10 sec. (Note 6) (Notes 1, 2) Storage Temperature If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VA, VD, VDR Supply Voltage (VA, VD) −0.3V to VA or VD +0.3V Input Current at Any Pin (Note 3) Package Input Current (Note 3) Package Dissipation at TA = 25˚C ± 25 mA ± 50 mA Machine Model (Note 5) +3.0V to +3.60V Output Driver Supply (VDR) +2.
PAGE 6
ADC12L063 DC and Logic Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = VDR = +3.3V, PD = 0V, VREF = +1.0V, fCLK = 62 MHz, tr = tf = 2 ns, CL = 20 pF/pin. Boldface limits apply for TA = TJ = TMIN to TMAX: all other limits TA = TJ = 25˚C (Notes 7, 8, 9) Symbol Parameter Conditions Typical (Note 10) Limits (Note 10) Units (Limits) 2.0 V(min) 0.
PAGE 7
(Continued) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = VDR = +3.3V, PD = 0V, VREF = +1.0V, fCLK = 62 MHz, tr = tf = 2 ns, CL = 20 pF/pin. Boldface limits apply for TA = TJ = TMIN to TMAX: all other limits TA = TJ = 25˚C (Notes 7, 8, 9) Symbol SFDR IMD Parameter Spurious Free Dynamic Range Intermodulation Distortion Conditions Typical (Note 10) Limits (Note 10) Units (Limits) fIN = 1 MHz, Differential VIN = −0.
PAGE 8
ADC12L063 AC Electrical Characteristics (Continued) 20026307 Note 8: To guarantee accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin. Note 9: With the test condition for VREF = +1.0V (2VP-P differential input), the 12-bit LSB is 488 µV. Note 10: Typical figures are at TA = TJ = 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
PAGE 9
APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for conversion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. Aperture jitter manifests itself as noise in the output. COMMON MODE VOLTAGE (VCM) is the d.c. potential present at both signal inputs to the ADC. CONVERSION LATENCY See PIPELINE DELAY.
PAGE 10
ADC12L063 Timing Diagram 20026309 Output Timing Transfer Characteristic 20026310 FIGURE 1. Transfer Characteristic www.national.
PAGE 11
VA = VD = VDR = 3.3V, fCLK = 62MHz, fIN = 10 MHz unless DNL vs. Clock Duty Cycle DNL vs. VA 20026360 20026359 DNL vs. Temperature INL vs. VA 20026358 20026362 INL vs. Clock Duty Cycle INL vs. Temperature 20026363 20026366 11 www.national.
PAGE 12
ADC12L063 Typical Performance Characteristics VA = VD = VDR = 3.3V, fCLK = 62MHz, fIN = 10 MHz unless otherwise stated (Continued) SNR vs. VA SNR vs. fCLK 20026364 20026368 SNR vs. Clock Duty Clock Cycle SNR vs. VREF 20026371 20026369 SNR vs. Temperature THD vs. VA 20026372 www.national.
PAGE 13
THD vs. fCLK THD vs. Clock Duty Cycle 20026377 20026374 THD vs. VREF THD vs. Temperature 20026378 20026375 SINAD vs. VA SINAD vs. fCLK 20026376 20026380 13 www.national.com ADC12L063 Typical Performance Characteristics VA = VD = VDR = 3.
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ADC12L063 Typical Performance Characteristics VA = VD = VDR = 3.3V, fCLK = 62MHz, fIN = 10 MHz unless otherwise stated (Continued) SINAD vs. Duty Cycle SINAD vs. VREF 20026383 20026381 SINAD vs. Temperature SFDR vs. VA 20026384 20026382 SFDR vs. fCLK SFDR vs. Duty Cycle 20026389 20026386 www.national.
PAGE 15
SFDR vs. VREF SFDR vs. Temperature 20026390 20026387 15 www.national.com ADC12L063 Typical Performance Characteristics VA = VD = VDR = 3.
PAGE 16
ADC12L063 1.2 Reference Pins The ADC12L063 is designed to operate with a 1.0V reference, but performs well with reference voltages in the range of 0.8V to 1.2V. Lower reference voltages will decrease the signal-to-noise ratio (SNR) of the ADC12L063. Increasing the reference voltage (and the input signal swing) beyond 1.2V will degrade THD for a full-scale input.
PAGE 17
The CLOCK signal also drives an internal state machine. If the clock is interrupted, or its frequency is too low, the charge on internal capacitors can dissipate to the point where the accuracy of the output data will degrade. The duty cycle of the clock signal can affect the performance of any A/D Converter. Because achieving a precise duty cycle is difficult, the ADC12L063 is designed to maintain performance over a range of duty cycles.
PAGE 18
ADC12L063 Applications Information (74ACQ541, for example). Only one input should be connected to each output pin. Additionally, inserting series resistors of 47Ω to 56Ω at the digital outputs, close to the ADC pins, will isolate the outputs from trace and other circuit capacitances and limit the output currents, which could otherwise result in performance degradation. See Figure 4. While the ADC12L063 will operate with VDR voltages down to 2.5V, tOD increases with reduced VDR.
PAGE 19
ADC12L063 Applications Information (Continued) 20026314 FIGURE 5. Differential Drive Circuit of Figure 4 20026315 FIGURE 6. Driving the Signal Inputs with a Transformer 19 www.national.
PAGE 20
ADC12L063 Applications Information exhibit high transients that could add noise to the conversion process. To prevent this from happening, the DR GND pins should NOT be connected to system ground in close proximity to any of the ADC12L063’s other ground pins. Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor performance.
PAGE 21
exhibit overshoot or undershoot that goes above the power supply or below ground. A resistor of about 50Ω to 100Ω in series with any offending digital input, close to the signal source, will eliminate the problem. (Continued) which they are used. Inductors should not be placed side by side, even with just a small part of their bodies beside each other. The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component (e.g.
PAGE 22
ADC12L063 12-Bit, 62 MSPS, 354 mW A/D Converter with Internal Sample-and-Hold Physical Dimensions inches (millimeters) unless otherwise noted 32-Lead LQFP Package Ordering Number ADC12L063CIVY NS Package Number VBE32A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1.