User Manual

Tables (Continued)
TABLE VII. Status Register
Status Bit
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8
Location
Status Bit PU PD Cal 8 or 9 12 or 13 16 or 17 Sign Justification Test Mode
Device Status DO Output Format Status
‘‘High’’ ‘‘High’’ ‘‘High’’ ‘‘High’’ ‘‘High’’ ‘‘High’’ ‘‘High’’ When ‘‘High’’ When
indicates indicates indicates indicates indicates indicates indicates the ‘‘High’’ the
a Power a Power an Auto- an 8 or 9 a 12 or a 16 or that the conversion device is in
Up Down Cal bit format 13 bit 17 bit sign bit is result will be test mode.
Function
Sequence Sequence Sequence format format included. output MSB When
is in is in is in When first. When ‘‘Low’’ the
progress progress progress ‘‘Low’’ ‘‘Low’’ the device is in
the sign result will be user mode.
bit is not output LSB
included. first.
Application Hints
1.0 DIGITAL INTERFACE
1.1 Interface Concepts
The example in
Figure 5 shows a typical sequence of
events after the power is applied to the ADC12L030/2/4/8:
TL/H/11830– 36
FIGURE 5. Typical Power Supply Power Up Sequence
The first instruction input to the A/D via DI initiates Auto Cal.
The data output on DO at that time is meaningless and is
completely random. To determine whether the Auto Cal has
been completed, a read status instruction is issued to the
A/D. Again the data output at that time has no significance
since the Auto Cal procedure modifies the data in the output
shift register. To retrieve the status information, an addition-
al read status instruction is issued to the A/D. At this time
the status data is available on DO. If the Cal signal in the
status word is low Auto Cal has been completed. Therefore,
the next instruction issued can start a conversion. The data
output at this time is again status information. To keep noise
from corrupting the A/D conversion, the status can not be
read during a conversion. If CS
is strobed and is brought low
during a conversion, that conversion is prematurely ended.
EOC can be used to determine the end of a conversion or
the A/D controller can keep track in software of when it
would be appropriate to communicate to the A/D again.
Once it has been determined that the A/D has completed a
conversion another instruction can be transmitted to the
A/D. The data from this conversion can be accessed when
the next instruction is issued to the A/D.
Note, when CS
is low continuously it is important to transmit
the exact number of SCLK cycles, as shown in the timing
diagrams. Not doing so will desynchronize the serial com-
munication to the A/D (see Section 1.3).
1.2 Changing Configuration
The configuration of the ADC12L030/2/4/8 on power up
defaults to 12-bit plus sign resolution, 12- or 13-bit MSB
First, 10 CCLK acquisition time, user mode, no Auto Cal, no
Auto Zero, and power up mode. Changing the acquisition
time and turning the sign bit on and off requires an 8-bit
instruction to be issued to the ADC. This instruction will not
start a conversion. The instructions that select a multiplexer
address and format the output data do start a conversion.
Figure 6 describes an example of changing the configura-
tion of the ADC12L030/2/4/8.
During I/O sequence 1 the instruction on DI configures the
ADC12L030/2/4/8 to do a conversion with 12-bit
a
sign
resolution. Notice that when the 6 CCLK Acquisition and
Data Out without Sign instructions are issued to the ADC,
I/O sequences 2 and 3, a new conversion is not started.
The data output during these instructions is from conversion
N which was started during I/O sequence 1. The Configura-
tion Modification timing diagram describes in detail the se-
quence of events necessary for a Data Out without Sign,
Data Out with Sign, or 6/10/18/34 CCLK Acquisition time
mode selection. Table V describes the actual data neces-
TL/H/11830– 37
FIGURE 6. Changing the ADC’s Conversion Configuration
25