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TL/H/11025

ADC12451 Dynamically-Tested Self-Calibrating 12-Bit

Plus Sign A/D Converter with Sample-and-Hold

December 1994

ADC12451 Dynamically-Tested Self-Calibrating

12-Bit Plus Sign A/D Converter with Sample-and-Hold

General Description

The ADC12451 is a CMOS 12-bit plus sign successive ap-

proximation analog-to-digital converter whose dynamic

specifications (S/N, THD, etc.) are tested and guaranteed.

On request, the ADC12451 goes through a self-calibration

cycle that adjusts linearity, zero and full-scale errors. The

ADC12451 also has the ability to go through an Auto-Zero

cycle that corrects the zero error during every conversion.

The analog input to the ADC12451 is tracked and held by

the internal circuitry, so an external sample-and-hold is not

required. The ADC12451 has a S

/H control input which di-

rectly controls the track-and-hold state of the A/D. A unipo-

lar analog input voltage range (0V to

5V) or a bipolar

range (

5V to

5V) can be accommodated with

5V sup-

plies.

The 13-bit data result is available on the eight outputs of the

ADC12451 in two bytes, high-byte first and sign extended.

The digital inputs and outputs are compatible with TTL or

CMOS logic levels.

Applications

Digital Signal Processing

Audio

Telecommunications

High Resolution Process Control

Instrumentation

Features

Self-calibration provides excellent temperature stability

Internal sample-and-hold

8-bit mP/DSP interface

Bipolar input range with a single

5V reference

Key Specifications

Resolution 12 bits plus sign

Conversion Time 7.7 ms (max)

Sampling Rate 83 kHz (max)

Bipolar Signal/Noise 73.5 dB (min)

Total Harmonic Distortion

78.0 dB (max)

Aperture Time 100 ns

Aperture Jitter 100 ps

rms

Zero Error

2 LSB (max)

Positive Full-Scale Error

1.5 LSB (max)

Power Consumption

5V 113 mW (max)

Simplified Block Diagram

TL/H/11025–1

Connection Diagram

Dual-In-Line Package

TL/H/11025–2

Top View

Ordering Information

Industrial

Package

(

ADC12451CIJ J24A

Military

Package

(

125

ADC12451CMJ,

J24A

ADC12451CMJ/883

TRI-STATE

is a registered trademark of National Semiconductor Corporation.

1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

Summary of content (18 pages)

PAGE 1
ADC12451 Dynamically-Tested Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold General Description The ADC12451 is a CMOS 12-bit plus sign successive approximation analog-to-digital converter whose dynamic specifications (S/N, THD, etc.) are tested and guaranteed. On request, the ADC12451 goes through a self-calibration cycle that adjusts linearity, zero and full-scale errors.
PAGE 2
Absolute Maximum Ratings (Notes 1 & 2) Operating Ratings (Notes 1 & 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Temperature Range ADC12451CIJ ADC12451CMJ, ADC12451CMJ/883 Supply Voltage (VCC e DVCC e AVCC) 6.5V b 6.5V Negative Supply Voltage (Vb) b 0.3V to (VCC a 0.3V) Voltage at Logic Control Inputs Voltage at Analog Inputs (VIN, VREF) (Vb b0.3V) to (VCC a 0.3V) 0.
PAGE 3
Converter Electrical Characteristics (Continued) The following specifications apply for VCC e DVCC e AVCC e a 5.0V, Vb e b5.0V, VREF e a 5.0V, using S/H input for conversion control, and fCLK e 3.5 MHz unless otherwise specified. Boldface limits apply for TA e TJ e TMIN to TMAX; all other limits TA e TJ e 25§ C.
PAGE 4
Digital and DC Electrical Characteristics The following specifications apply for DVCC e AVCC e a 5.0V, Vb e b5.0V, VREF e a 5.0V, and fCLK e 3.5 MHz unless otherwise specified. Boldface limits apply for TA e TJ e TMIN to TMAX; all other limits TA e TJ e 25§ C. (Notes 6 and 7) Symbol Parameter Condition Typical (Note 9) Limit (Note 10, 19) Units (Limit) VIN(1) Logical ‘‘1’’ Input Voltage for All Inputs except CLK IN VCC e 5.25V 2.
PAGE 5
AC Electrical Characteristics (Continued) The following specifications apply for DVCC e AVCC e a 5.0V, Vb e b5.0V, tr e tf e 20 ns unless otherwise specified. Boldface limits apply for TA e TJ e TMIN to TMAX; all other limits TA e TJ e 25§ C.
PAGE 6
Electrical Characteristics (Continued) Note 7: A diode exists between AVCC and DVCC as shown below. TL/H/11025 – 5 To guarantee accuracy, it is required that the AVCC and DVCC be connected together to a power supply with separate bypass filters at each VCC pin. Note 8: Accuracy is guaranteed at fCLK e 3.5 MHz. At higher or lower clock frequencies accuracy may degrade, see the typical performance characteristic curves. Note 9: Typicals are at TJ e 25§ C and represent most likely parametric norm.
PAGE 7
Electrical Characteristics (Continued) TL/H/11025 – 7 FIGURE 1b. Simplified Error Curve vs Output Code without Auto-Cal or Auto-Zero Cycles TL/H/11025 – 8 FIGURE 1c.
PAGE 8
Typical Performance Characteristics (Continued) Linearity Error vs Clock Frequency Full Scale Error Change vs Ambient Temperature Bipolar Signal-toNoise a Distortion Ratio vs Input Source Impedance Bipolar Signal-toNoise a Distortion Ratio vs Input Frequency Unipolar Signal-toNoise a Distortion Ratio vs Input Frequency Unipolar Signal-toNoise a Distortion Ratio vs Input Signal Level Bipolar Signal-toNoise a Distortion Ratio vs Input Signal Level Bipolar Spectral Response with 1 kHz Sine Wave Input
PAGE 9
Typical Performance Characteristics Unipolar Spectral Response with 10 kHz Sine Wave Input (Continued) Unipolar Spectral Response with 20 kHz Sine Wave Input Unipolar Spectral Response with 40 kHz Sine Wave Input TL/H/11025 – 11 Test Circuits TL/H/11025 – 13 TL/H/11025 – 12 TL/H/11025 – 15 TL/H/11025 – 14 FIGURE 2.
PAGE 10
Timing Diagrams Auto-Cal Cycle TL/H/11025 – 16 Using WR Control to Start a Conversion with Auto-Zero (CAL e 1, AZ e 0) TL/H/11025 – 17 10
PAGE 11
Timing Diagrams (Continued) Using WR Control to Start a Conversion without Auto-Zero (CAL 1, AZ e 1) TL/H/11025 – 18 Using S/H Control to Start a Conversion without Auto-Zero (AZ e 1, CAL e 1) TL/H/11025 – 19 11
PAGE 12
1.0 Pin Descriptions DVCC (24), AVCC (4) V b (5) DGND (12), AGND (3) VREF (2) VIN (1) The digital and analog positive power supply pins. The digital and analog power supply voltage range of the ADC12451 is a 4.5V to a 5.5V. To guarantee accuracy, it is required that the AVCC and DVCC be connected together to the same power supply with separate bypass capacitors (10 mF tantalum in parallel with a 0.1 mF ceramic) at each VCC pin. The analog negative supply voltage pin. Vb has a range of b4.5V to b5.
PAGE 13
2.0 Functional Description (Continued) the operation of the ADC12451. Care should be taken not to inadvertently be in this mode, since DB2, DB3, DB5, and DB6 become active outputs, which may cause data bus contention. A conversion sequence can also be controlled by the S/H and CS inputs. Taking CS and S/H low starts the acquisition window for the analog input voltage. The rising edge of S/H immediately puts the A/D in the hold mode and starts the conversion.
PAGE 14
3.0 Analog Considerations (Continued) TL/H/11025 – 21 TL/H/11025 – 20 FIGURE 4a. Low Drift Extremely Stable Reference Circuit Errors without any trims: b 40§ C to a 85§ C 25§ C g 0.075% g 0.2% Full Scale g 0.024% g 0.024% Zero g (/2 LSB g (/2 LSB Linearity FIGURE 4b. Simple Reference Circuit this method the acquisition window is internally controlled by the ADC12451 and lasts for approximately 7 clock periods. Since the acquisition window needs to be at least 3.
PAGE 15
3.0 Analog Considerations (Continued) change. Since Auto-Zero cannot be activated with S/H conversion method it may be necessary to do a calibration cycle more than once. 3.5 INPUT BYPASS CAPACITORS An external capacitor can be used to filter out any noise due to inductive pickup by a long input lead and will not degrade the accuracy of the conversion result. 3.9 THE AUTO-ZERO CYCLE To correct for any change in the zero (offset) error of the A/D, the auto-zero cycle can be used.
PAGE 16
4.0 Dynamic Performance (Continued) Two sample/hold specifications, aperture time and aperture jitter, are included in the Dynamic Characteristics table since the ADC12451 has the ability to track and hold the analog input voltage. Aperture time is the delay for the A/D to respond to the hold command. In the case of the ADC12451, the hold command is internally generated.
PAGE 17
PAGE 18
ADC12451 Dynamically-Tested Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold Physical Dimensions inches (millimeters) Order Number ADC12451CMJ, ADC12451CMJ/883 or ADC12451CIJ NS Package Number J24A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1.