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TL/H/11490

ADC12062 12-Bit, 1 MHz, 75 mW A/D Converter

with Input Multiplexer and Sample/Hold

December 1994

ADC12062

12-Bit, 1 MHz, 75 mW A/D Converter

with Input Multiplexer and Sample/Hold

General Description

Using an innovative multistep conversion technique, the

12-bit ADC12062 CMOS analog-to-digital converter digitizes

signals at a 1 MHz sampling rate while consuming a maxi-

mum of only 75 mW on a single

5V supply. The

ADC12062 performs a 12-bit conversion in three lower-res-

olution ‘‘flash’’ conversions, yielding a fast A/D without the

cost and power dissipation associated with true flash ap-

proaches.

The analog input voltage to the ADC12062 is tracked and

held by an internal sampling circuit, allowing high frequency

input signals to be accurately digitized without the need for

an external sample-and-hold circuit. The multiplexer output

is available to the user in order to perform additional exter-

nal signal processing before the signal is digitized.

When the converter is not digitizing signals, it can be placed

in the Standby mode; typical power consumption in this

mode is 100 mW.

Features

Built-in sample-and-hold

Single

5V supply

Single channel or 2 channel multiplexer operation

Low Power Standby mode

Key Specifications

Sampling rate 1 MHz (min)

Conversion time 740 ns (typ)

Signal-to-Noise Ratio, f

100 kHz 69.5 dB (min)

Power dissipation (f

1 MHz) 75 mW (max)

No missing codes over temperature Guaranteed

Applications

Digital signal processor front ends

Instrumentation

Disk drives

Mobile telecommunications

Waveform digitizers

Block Diagram

TL/H/11490– 1

Ordering Information

Industrial (

) Package

ADC12062BIV V44 Plastic Leaded Chip Carrier

ADC12062BIVF VGZ44A Plastic Quad Flat Package

ADC12062CIV V44 Plastic Leaded Chip Carrier

ADC12062CIVF VGZ44A Plastic Quad Flat Package

ADC12062EVAL Evaluation Board

TRI-STATE

is a registered trademark of National Semiconductor Corporation.

1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.

Summary of content (20 pages)

PAGE 1
ADC12062 12-Bit, 1 MHz, 75 mW A/D Converter with Input Multiplexer and Sample/Hold General Description Features Using an innovative multistep conversion technique, the 12-bit ADC12062 CMOS analog-to-digital converter digitizes signals at a 1 MHz sampling rate while consuming a maximum of only 75 mW on a single a 5V supply.
PAGE 2
Absolute Maximum Ratings (Notes 1, 2) Soldering Information (Note 6) V Package, Infrared, 15 seconds VF Package Vapor Phase (60 seconds) Infrared (15 seconds) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC e DVCC e AVCC) Voltage at Any Input or Output Input Current at Any Pin (Note 3) Package Input Current (Note 3) Power Dissipation (Note 4) ESD Susceptibility (Note 5) b 0.
PAGE 3
Dynamic Characteristics (Note 10) The following specifications apply for DVCC e AVCC e a 5V, VREF a (SENSE) e a 4.096V, VREFb(SENSE) e AGND, RS e 25X, fIN e 100 kHz, 0 dB from fullscale, and fs e 1 MHz, unless otherwise specified. Boldface limits apply for TA e TJ from TMIN to TMAX; all other limits TA e TJ e a 25§ C. Symbol Parameter Conditions Typ (Note 7) Limit (Note 8) Units (Limit) SINAD Signal-to-Noise Plus Distortion Ratio TMIN to TMAX 71 68.
PAGE 4
AC Electrical Characteristics The following specifications apply for DVCC e AVCC e a 5V, VREF a (SENSE) e a 4.096V, VREFb(SENSE) e AGND, and fs e 1 MHz, unless otherwise specified. Boldface limits apply for TA e TJ from TMIN to TMAX; all other limits TA e TJ e a 25§ C.
PAGE 5
Note 5: Human body model, 100 pF discharged through a 1.5 kX resistor. Machine model ESD rating is 200V. Note 6: See AN-450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ or the section titled ‘‘Surface Mount’’ found in a current National Semiconductor Linear Data Book for other methods of soldering surface mount devices. Note 7: Typicals are at a 25§ C and represent most likely parametric norm. Note 8: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
PAGE 6
Typical Performance Characteristics Offset and Fullscale Error Change vs Reference Voltage Linearity Error Change vs Reference Voltage Mux ON Resistance vs Input Voltage Digital Supply Current vs Temperature Analog Supply Current vs Temperature Current Consumption in Standby Mode vs Voltage on Digital Input Pins Conversion Time (tCONV) vs Temperature EOC Delay Time (tEOC) vs Temperature Spectral Response SINAD vs Input Frequency (ADC IN) SNR vs Input Frequency (ADC IN) THD vs Input Frequency (ADC
PAGE 7
Typical Performance Characteristics SINAD vs Input Frequency (Through Mux) (Continued) SNR vs Input Frequency (Through Mux) SNR and THD vs Source Impedance THD vs Input Frequency (Through Mux) SNR and THD vs Reference Voltage TL/H/11490 – 28 Timing Diagrams TL/H/11490 – 9 FIGURE 1.
PAGE 8
Timing Diagrams (Continued) TL/H/11490 – 10 FIGURE 2. High Speed Interface Timing (MODE e 1, OE e 1, CS e 0, RD e 0) TL/H/11490 – 11 FIGURE 3.
PAGE 9
Pin Descriptions AVCC DVCC AGND, DGND1, DGND2 DB0 – DB11 VIN1, VIN2 MUX OUT ADC IN S0 These are the two positive analog supply inputs. They should always be connected to the same voltage source, but are brought out separately to allow for separate bypass capacitors. Each supply pin should be bypassed to AGND with a 0.1 mF ceramic capacitor in parallel with a 10 mF tantalum capacitor. This is the positive digital supply input.
PAGE 10
Functional Description The ADC12062 performs a 12-bit analog-to-digital conversion using a 3 step flash technique. The first flash determines the six most significant bits, the second flash generates four more bits, and the final flash resolves the two least significant bits. Figure 4 shows the major functional blocks of the converter.
PAGE 11
Functional Description (Continued) tap points between (*/8)VREF and (±/8)VREF. This overlap of ((/16)VREF will automatically cancel a Voltage Estimator error of up to 256 LSBs. If the first flash conversion determines that the input voltage is between (*/8)VREF and ((%/8)VREF b LSB/2), the Voltage Estimator’s output code will be corrected by subtracting ‘‘1’’, resulting in a corrected value of ‘‘01’’ for the first two MSBs.
PAGE 12
Applications Information (Continued) TL/H/11490 – 16 FIGURE 6. ADC Control Logic For maximum performance, the impedance of the source driving the ADC12062 should be made as small as possible. A source impedance of 100X or less is recommended. A plot of dynamic performance vs. source impedance is given in the Typical Performance Characteristics section.
PAGE 13
Applications Information (Continued) TL/H/11490 – 18 FIGURE 8. Buffering the Input with an LM6361 High Speed Op Amp Another benefit of using a high speed buffer is improved THD performance when using the multiplexer of the ADC12062. The MUX on-resistance is somewhat non-linear over input voltage, causing the RC time constant formed by CIN, RMUX, and RSW to vary depending on the input voltage. This results in increasing THD with increasing frequency.
PAGE 14
Applications Information (Continued) signal is returned to the ADC IN input and digitized. If no additional signal processing is required, the MUX OUT pin should be tied directly to the ADC IN pin. See Section 9.0 (APPLICATIONS) for a simple circuit that will alternate between the two inputs while converting at full speed. 3.0 ANALOG MULTIPLEXER The ADC12062 has an input multiplexer that is controlled by the logic level on pin S0 when EOC goes low, as shown in Figures 1 and 2.
PAGE 15
Applications Information (Continued) The reference inputs are fully differential and define the zero to full-scale range of the input signal. They can be configured to span up to 5V (VREFb e 0V, VREF a e 5V), or they can be connected to different voltages (within the 0V to 5V limits) when other input spans are required. The ADC12062 is tested at VREFb (SENSE) e 0V, VREF a (SENSE) e 4.096V.
PAGE 16
Applications Information (Continued) 5.0 POWER SUPPLY CONSIDERATIONS The ADC12062 is designed to operate from a single a 5V power supply. There are two analog supply pins (AVCC) and one digital supply pin (DVCC). These pins allow separate external bypass capacitors for the analog and digital portions of the circuit. To guarantee proper operation of the converter, all three supply pins should be connected to the same voltage source.
PAGE 17
Applications Information (Continued) converter is turned off, but other devices connected to it (op amps, microprocessors) still have power. Note that if there is no power to the converter, DGND e AGND e DVCC e AVCC e 0V, so all inputs should be within g 300 mV of AGND and DGND. Driving a high capacitance digital data bus. The more capacitance the data bus has to charge for each conversion, the more instantaneous digital current required from DVCC and DGND.
PAGE 18
Applications Information (Continued) AC Coupling Bipolar Inputs TL/H/11490 – 26 18
PAGE 19
Physical Dimensions inches (millimeters) Plastic Leaded Chip Carrier (V) Order Number ADC12062BIV, ADC12062CIV NS Package Number V44A 19
PAGE 20
ADC12062 12-Bit, 1 MHz, 75 mW A/D Converter with Input Multiplexer and Sample/Hold Physical Dimensions inches (millimeters) (Continued) Plastic Quad Flat Package (VF) Order Number ADC12062BIVF, ADC12062CIVF NS Package Number VGZ44A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1.