Owner manual
Table Of Contents
- ADC1175
- General Description
- Features
- Key Specifications
- Applications
- Pin Configuration
- Ordering Information
- Block Diagram
- Pin Descriptions and Equivalent Circuits
- Absolute Maximum Ratings
- Operating Ratings(Notes , )
- Converter Electrical Characteristics
- Typical Performance Characteristics
- Specification Definitions
- Timing Diagram
- FIGURE 2. tEN, tDISTest Circuit
- Functional Description
- Applications Information
- 1.0 THE ANALOG INPUT
- 2.0 REFERENCE INPUTS
- FIGURE 3. Simple, Low Component Count, Self -Bias Reference application. Because of resistor toleran
- FIGURE 4. Better defining the ADC Reference Voltage. Self-bias is still used, but the reference volt
- FIGURE 5. Driving the reference to force desired values requires driving with a low impedance source
- 3.0 POWER SUPPLY CONSIDERATIONS
- 4.0 THE ADC1175 CLOCK
- 5.0 LAYOUT AND GROUNDING
- FIGURE 6. Layout example showing separate analog and digital ground planes connected below the ADC11
- 6.0 DYNAMIC PERFORMANCE
- FIGURE 7. Isolating the ADC clock from Digital Circuitry.
- 7.0 COMMON APPLICATION PITFALLS
- FIGURE 8. 5.5 MHz Low Pass Filter to Eliminate Harmonics at the Signal Input.
- FIGURE 9. 11 MHz Low Pass filter to eliminate harmonics at the signal input. Use at input frequencie
- Physical Dimensions
Converter Electrical Characteristics (Continued)
The following specifications apply for AV
DD
=DV
DD
= +5.0V
DC
, OE = 0V, V
RT
= +2.6V, V
RB
= 0.6V, C
L
= 20 pF,
f
CLK
= 20MHz at 50% duty cycle. Boldface limits apply for T
A
=T
MIN
to T
MAX
; all other limits T
A
= 25˚C (Notes 7, 8)
Symbol Parameter Conditions
Typical
(Note 9)
Limits
(Note 9)
Units
V
RT
Reference Top Self Bias
Voltage
V
RT
connected to V
RTS
V
RB
connected to V
RBS
2.6 V
V
RB
Reference Bottom Self Bias
Voltage
V
RT
connected to V
RTS
0.6
0.55 V(min)
V
RB
connected to V
RBS
0.65 V(max)
V
RTS
-
V
RBS
Self Bias Voltage Delta
V
RT
connected to V
RTS
,
V
RB
connected to V
RBS
2
1.89
2.15
µAmin
µAmax
V
RT
connected to V
RTS
,
V
RB
connected to AV
SS
2.3 V
V
RT
-V
RB
Reference Voltage Delta 2
1.0 V(min)
2.8 V(max)
Power Supply Characteristics
IA
DD
Analog Supply Current DV
DD
=AV
DD
=5.25V 9.5 mA
ID
DD
Digital Supply Current DV
DD
=AV
DD
=5.25V 2.5 mA
IAV
DD
+
IDV
DD
Total Operating Current
DV
DD
AV
DD
=5.25V, f
CLK
= 20 MHz 12 17 mA
DV
DD
AV
DD
=5.25V, f
CLK
= 30 MHz 13
DV
DD
=AV
DD
=5.25V, CLK Low
(Note 10)
9.6 mA
Power Consumption
DV
DD
=AV
DD
=5.25V, f
CLK
= 20 MHz 60 85 mW
DV
DD
=AV
DD
=5.25V, f
CLK
= 30 MHz 65 mW
CLK, OE Digital Input Characteristics
V
IH
Logical High Input Voltage DV
DD
=AV
DD
= +5.25V 3.0 V (min)
V
IL
Logical Low Input Voltage DV
DD
=AV
DD
= +5.25V 1.0 V (max)
I
IH
Logical High Input Current V
IH
=DV
DD
=AV
DD
= +5.25V 5 µA
I
IL
Logic Low Input Current V
IL
= 0V, DV
DD
=AV
DD
= +5.25V −5 µA
C
IN
Logic Input Capacitance 5 pF
Digital Output Characteristics
I
OH
High Level Output Current DV
DD
= 4.75V, V
OH
= 2.4V −1.1 mA (min)
I
OL
Low Level Output Current DV
DD
= 4.75V, V
OL
= 0.4V 1.6 mA (max)
I
OZH
,
I
OZL
Tri-State
®
Leakage Current
DV
DD
= 5.25V
OE=DV
DD
,V
OL
=0VorV
OH
=DV
DD
±
20 µA
AC Electrical Characteristics
f
C1
Maximum Conversion Rate 30 20 MHz(min)
f
C2
Minimum Conversion Rate 1 MHz
t
OD
Output Delay CLK high to data valid 19 ns(max)
Pipeline Delay (Latency) 2.5
Clock
Cycles
t
DS
Sampling (Aperture) Delay CLK low to acquisition of data 3 ns
t
AJ
Aperture Jitter 30 ps rms
t
OH
Output Hold Time CLK high to data invalid 10 ns
t
EN
OE Low to Data Valid Loaded as in Figure 2 11 ns
t
DIS
OE High to High Z State Loaded as in Figure 2 15 ns
ENOB Effective Number of Bits
f
IN
= 1.31 MHz, V
IN
=FS-2LSB
f
IN
= 4.43 MHz, V
IN
=FS-2LSB
f
IN
= 9.9 MHz, V
IN
=FS-2LSB
f
IN
= 4.43 MHz, f
CLK
= 30 MHz
7.5
7.3
7.2
6.5
7.0
Bits (min)
ADC1175
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