Owner manual
Table Of Contents
- ADC1175
- General Description
- Features
- Key Specifications
- Applications
- Pin Configuration
- Ordering Information
- Block Diagram
- Pin Descriptions and Equivalent Circuits
- Absolute Maximum Ratings
- Operating Ratings(Notes , )
- Converter Electrical Characteristics
- Typical Performance Characteristics
- Specification Definitions
- Timing Diagram
- FIGURE 2. tEN, tDISTest Circuit
- Functional Description
- Applications Information
- 1.0 THE ANALOG INPUT
- 2.0 REFERENCE INPUTS
- FIGURE 3. Simple, Low Component Count, Self -Bias Reference application. Because of resistor toleran
- FIGURE 4. Better defining the ADC Reference Voltage. Self-bias is still used, but the reference volt
- FIGURE 5. Driving the reference to force desired values requires driving with a low impedance source
- 3.0 POWER SUPPLY CONSIDERATIONS
- 4.0 THE ADC1175 CLOCK
- 5.0 LAYOUT AND GROUNDING
- FIGURE 6. Layout example showing separate analog and digital ground planes connected below the ADC11
- 6.0 DYNAMIC PERFORMANCE
- FIGURE 7. Isolating the ADC clock from Digital Circuitry.
- 7.0 COMMON APPLICATION PITFALLS
- FIGURE 8. 5.5 MHz Low Pass Filter to Eliminate Harmonics at the Signal Input.
- FIGURE 9. 11 MHz Low Pass filter to eliminate harmonics at the signal input. Use at input frequencie
- Physical Dimensions
Pin Descriptions and Equivalent Circuits (Continued)
Pin
No. Symbol Equivalent Circuit
Description
17 V
RT
Analog Input that is the high (top) side of the
reference ladder of the ADC. Nominal range is 1.0V
to AV
DD
. Voltage on V
RT
and V
RB
inputs define the
V
IN
conversion range. Bypass well. See Section 2.0
for more information.
23 V
RB
Analog Input that is the low (bottom) side of the
reference ladder of the ADC. Nominal range is 0V to
4.0V. Voltage on V
RT
and V
RB
inputs define the V
IN
conversion range. Bypass well. See Section 2.0 for
more information.
22 V
RBS
Reference Bottom Bias with internal pull down
resistor. Short to V
RB
to self bias the reference
ladder.
1OE
CMOS/TTL compatible Digital input that, when low,
enables the digital outputs of the ADC1175. When
high, the outputs are in a high impedance state.
12 CLK
CMOS/TTL compatible digital clock Input. V
IN
is
sampled on the falling edge of CLK input.
3 thru
10
D0-D7
Conversion data digital Output pins. D0 is the LSB,
D7 is the MSB. Valid data is output just after the
rising edge of the CLK input. These pins are enabled
by bringing the OE pin low.
11, 13 DV
DD
Positive digital supply pin. Connect to a clean, quiet
voltage source of +5V. AV
DD
and DV
DD
should have
a common source and be separately bypassed with a
10µF capacitor and a 0.1µF ceramic chip capacitor.
See Section 3.0 for more information.
ADC1175
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