Timing Diagrams (Continued)
TL/H/11390–21
FIGURE 9. ADC10731 Using CS to Delay Output of Data afer a Conversion has Completed
Note: If CS is low during power up of the power supply voltages (AV
a
and DV
a
) then CS needs to go high for t
CS(H)
. The data output after the first conversion is not valid.
16
