Instruction Manual

TRI-STATE Test Circuits and Waveforms
t
1H
t
0H
TL/H/10749–7
t
1H
t
0H
TL/H/10749–8
Timing Diagrams
Data Input Timing
TL/H/10749–9
*To reset these devices, CLK and CS must be simultaneously high for a period of t
SELECT
or greater. Otherwise these devices are compatible with industry
standards ADC0831/4/8.
Data Output Timing
TL/H/10749–10
ADC08131 Start Conversion Timing
TL/H/10749–11
8