Manual
Table Of Contents
- Pin Configuration
- Features
- Description
- Block Diagram
- Pin Description
- Oscillator Characteristics
- Special Function Registers
- Restrictions on Certain Instructions
- Program Memory Lock Bits
- Lock Bit Protection Modes(1)
- Idle Mode
- Power-down Mode
- Programming The Flash
- Programming Interface
- Flash Programming Modes
- Flash Programming and Verification Characteristics
- Flash Programming and Verification Waveforms
- Absolute Maximum Ratings*
- DC Characteristics
- External Clock Drive Waveforms
- External Clock Drive
- Serial Port Timing: Shift Register Mode Test Conditions
- Shift Register Mode Timing Waveforms
- AC Testing Input/Output Waveforms(1)
- Float Waveforms(1)
- Ordering Information
AT89C2051
7
Notes: 1. The internal PEROM address counter is reset to 000H on the rising edge of RST and is advanced by a positive pulse at
XTAL 1 pin.
2. Chip Erase requires a 10 ms PROG
pulse.
3. P3.1 is pulled Low during programming to indicate RDY/BSY
.
Figure 3. Programming the Flash Memory Figure 4. Verifying the Flash Memory
Flash Programming Modes
Mode RST/VPP P3.2/PROG P3.3 P3.4 P3.5 P3.7
Write Code Data
(1)(3)
12V L H H H
Read Code Data
(1)
HHLLHH
Write Lock Bit - 1 12V H H H H
Bit - 2 12V H H L L
Chip Erase 12V H L L L
Read Signature Byte H H L L L L
(2)
PP