User's Guide

Revision 1.0 Page 59 of 75
nRF24L01+ Preliminary Product Specification
N/A ACK_PLD 255:0 X W Written by separate SPI command
ACK packet payload to data pipe number PPP
given in SPI command.
Used in RX mode only.
Maximum three ACK packet payloads can be
pending. Payloads with same PPP are handled
first in first out.
N/A TX_PLD 255:0 X W Written by separate SPI command TX data pay-
load register 1 - 32 bytes.
This register is implemented as a FIFO with three
levels.
Used in TX mode only.
N/A RX_PLD 255:0 X R Read by separate SPI command.
RX data payload register. 1 - 32 bytes.
This register is implemented as a FIFO with three
levels.
All RX channels share the same FIFO.
1C DYNPD Enable dynamic payload length
Reserved 7:6 0 R/W Only ‘00’ allowed
DPL_P5 5 0 R/W Enable dynamic payload length data pipe 5.
(Requires
EN_DPL and ENAA_P5)
DPL_P4 4 0 R/W Enable dynamic payload length data pipe 4.
(Requires
EN_DPL and ENAA_P4)
DPL_P3 3 0 R/W Enable dynamic payload length data pipe 3.
(Requires
EN_DPL and ENAA_P3)
DPL_P2 2 0 R/W Enable dynamic payload length data pipe 2.
(Requires
EN_DPL and ENAA_P2)
DPL_P1 1 0 R/W Enable dynamic payload length data pipe 1.
(Requires
EN_DPL and ENAA_P1)
DPL_P0 0 0 R/W Enable dynamic payload length data pipe 0.
(Requires
EN_DPL and ENAA_P0)
1D FEATURE R/W Feature Register
Reserved 7:3 0 R/W Only ‘00000’ allowed
EN_DPL 2 0 R/W Enables Dynamic Payload Length
EN_ACK_PAY
d
1 0 R/W Enables Payload with ACK
EN_DYN_ACK 0 0 R/W Enables the W_TX_PAYLOAD_NOACK command
a. Please take care when setting this parameter. If the ACK payload is more than 15 byte in 2Mbps mode the
ARD must be 500µS or more, if the ACK payload is more than 5byte in 1Mbps mode the ARD must be
500µS or more. In 250kbps mode (even when the payload is not in ACK) the ARD must be 500µS or more.
b. This is the time the PTX is waiting for an ACK packet before a retransmit is made. The PTX is in RX mode
for a minimum of 250µS, but it stays in RX mode to the end of the packet if that is longer than 250µS. Then
it goes to standby-I mode for the rest of the specified ARD. After the ARD it goes to TX mode and then
retransmits the packet.
c. The
RX_DR IRQ is asserted by a new packet arrival event. The procedure for handling this interrupt should
be: 1) read payload through SPI, 2) clear
RX_DR IRQ, 3) read FIFO_STATUS to check if there are more
payloads available in RX FIFO, 4) if there are more data in RX FIFO, repeat from step 1).
Address
(Hex)
Mnemonic Bit
Reset
Value
Type Description