User's Guide

Revision 1.0 Page 47 of 75
nRF24L01+ Preliminary Product Specification
8 Data and Control Interface
The data and control interface gives you access to all the features in the nRF24L01+. The data and control
interface consists of the following six 5Volt tolerant digital signals:
•
IRQ (this signal is active low and controlled by three maskable interrupt sources)
•
CE (this signal is active high and used to activate the chip in RX or TX mode)
•
CSN (SPI signal)
•
SCK (SPI signal)
•
MOSI (SPI signal)
•
MISO (SPI signal)
Using 1 byte SPI commands, you can activate the nRF24L01+ data FIFOs or the register map during all
modes of operation.
8.1 Features
• Special SPI commands for quick access to the most frequently used features
• 0-10Mbps 4-wire SPI
• 8 bit command set
• Easily configurable register map
• Full three level FIFO for both TX and RX direction
8.2 Functional description
The SPI is a standard SPI with a maximum data rate of 10Mbps.
8.3 SPI operation
This section describes the SPI commands and timing.
8.3.1 SPI Commands
The SPI commands are shown in Table 19. Every new command must be started by a high to low transi-
tion on
CSN.
The
STATUS register is serially shifted out on the MISO pin simultaneously to the SPI command word shift-
ing to the
MOSI pin.
The serial shifting SPI commands is in the following format:
<
Command word: MSBit to LSBit (one byte)>
<
Data bytes: LSByte to MSByte, MSBit in each byte first>
See Figure 23. on page 49
and Figure 24. on page 49 for timing information.