Specifications

Connectors
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-SMEMW (O) -MEMW (I/O)
These signals instruct the memory devices to store the data present on the data bus. -
SMEMW is active only when the memory decode is within the low 1M of the
memory space. -MEMW is active on all memory write cycles. -MEMW may be
driven by any microprocessor or DMA controller in the system. -SMEMW is derived
from -MEMW and the decode of the low 1M of memory. When a microprocessor on
the I/O channel wishes to drive -MEMW, it must have the address lines valid on the
bus for one clock cycle before driving -MEMW active. Both signals are active low.
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TC (O)
The 'terminal count' signal provides a high pulse when the terminal count for any
DMA channel is reached.