Specifications

EPC-4 Hardware Reference

Page 26

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SA0 through SA23 (I/O)

Address signals 0 through 23 are used to address memory and I/O devices within the

system. These 24 address lines, in addition to LA17 through LA23, allow access of

up to 16M of memory. SA0 through SA23 are gated on the system bus when

'buffered address latch enable' signal (BALE) is high and are latched on the falling

edge of BALE. These signals are generated by the microprocessor or DMA

controller. They also may be driven by other microprocessors or DMA controllers

that reside on the I/O channel.

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-SBHE (I/O)

The '-system bus high enable' signal indicates a transfer of data on the upper byte of

the data bus, SD8 through SD15. 16-bit devices use -SBHE to condition data bus

buffers tied to SD8 through SD15. This signal is active low.

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SD0 through SD15 (I/O)

These signals provide bus bits 0 through 15 for the microprocessor, memory, and I/O

devices. D0 is the least-significant bit and D15 is the most-significant bit. All 8-bit

devices on the I/O channel should use D0 through D7 for communications to the

microprocessor. The 16-bit devices will use D0 through D15. To support 8-bit

devices, the data on D8 through D15 will be gated to D0 through D7 during 8-bit

transfers to these devices; 16-bit microprocessor transfers to 8-bit devices will be

converted to two 8-bit transfers.

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-SMEMR (O) -MEMR (I/O)

These signals instruct the memory devices to drive data onto the data bus.

-SMEMR is active only when the memory decode is within the low 1M of memory

space. -MEMR is active on all memory read cycles. -MEMR may be driven by any

microprocessor or DMA controller in the system. -SMEMR is derived from

-MEMR and the decode of the low 1M of memory. When a microprocessor on the

I/O channel wishes to drive -MEMR, it must have the address lines valid on the bus

for one clock cycle before driving -MEMR active. Both signals are active low.