Specifications

EPC-4 Hardware Reference
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-IOW (I/O)
The '-I/O write' signal instructs an I/O device to read the data off the data bus. It may
be driven by any microprocessor or DMA controller in the system. This signal is
active low.
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IRQ3 through IRQ7, IRQ9, IRQ11, IRQ12, IRQ14, & IRQ15 (I)
Interrupt requests 3 through 7, 9, 11, 12, 14, and 15 are used to signal the
microprocessor that an I/O device needs attention. The interrupt requests are
prioritized, with IRQ9, IRQ11, IRQ12, IRQ14 and IRQ15 having the highest priority
(IRQ9 is the highest), and IRQ3 through IRQ7 having the lowest priority (IRQ7 is the
lowest). An interrupt request is generated when an IRQ line is raised from low to
high. The line is high until the microprocessor acknowledges the interrupt request
(Interrupt service routine).
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-MEMCS16 (I)
The '-memory 16-bit chip select' signal indicates to the system that the present data
transfer is a 16-bit memory cycle. It must be derived from the decode of LA17
through LA23. -MEMCS16 is active low and should be driven with an open
collector or tri-state driver capable of sinking 20 mA.
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OSC (O)
The 'oscillator' signal is a high-speed clock with a 70-nanosecond period (14.31818
MHz). This signal is not synchronous with the system clock. It has a 50% duty
cycle.
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-REFRESH (I/O)
This signal is used to indicate a refresh cycle and can be driven by a microprocessor
on the I/O channel. This signal is active low.
-RESETIN (I)
This signal is used to provide an external reset signal to the system. It is an active
low signal.