Specifications

Connectors
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are prioritized, with DRQ0 having the highest priority and DRQ6 the lowest. A
request is generated by bringing a DRQ line to an active (high) level. A DRQ line is
held high until the corresponding 'DMA acknowledge' (DACK) line goes active.
DRQ0 through DRQ3 perform 8-bit DMA transfers, DRQ5 and DRQ6 perform 16-
bit transfers. DRQ4 is used on the system board and is not available on the I/O
channel.
-EXTSMI (I)
System management interrupt. Non-maskable. This is the highest priority interrupt
even taking priority over NMI. See the Intel386 SL Programming Reference for
details. This is an active low signal.
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-I/OCHK (I)
The 'I/O channel check' signal provides the system board with parity (error)
information about memory or devices on the I/O channel. When this signal is active
(low), it indicates a non-correctable system error.
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-
I/OCHRDY (I)
The 'I/O channel ready' signal is pulled low (not ready) by a memory or I/O device to
lengthen I/O or memory cycles. Any slow device using this line should drive it low
immediately upon detecting its valid address and a Read or Write command.
Machine cycles are extended by an integral number of clock cycles (125
nanoseconds). This signal should be held low for no more than 2.5 microseconds.
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-I/OCS16 (I)
The 'I/O 16-bit chip select' signal indicates to the system that the present data transfer
is a 16-bit I/O cycle. It is derived from an address decode.
-I/OCS16 is active low and should be driven with an open collector or tri-state driver
capable of sinking 20 mA.
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-IOR (I/O)
The '-I/O read' signal instructs an I/O device to drive its data onto the data bus. This
signal may be driven by the system microprocessor or DMA controller, or by a
microprocessor or DMA controller resident on the I/O channel. This signal is active
low.