Specifications

EPC-4 Hardware Reference
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device with a minimum of two wait states, 0WS should be driven active one clock
cycle after the Read or Write command is active, and gated with the address decode
for the device. Memory Read and Write commands to an 8-bit device are active on
the falling edge of CLK. 0WS is active low and should be driven with an open
collector or tri-state driver capable of sinking 20 mA.
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AEN (O)
The 'address enable' signal is used to de-gate the microprocessor and other devices
from the I/O channel to allow DMA transfers to take place. When this line is active,
the DMA controller has control of the address bus, the data-bus Read command lines
(memory and I/O), and the Write command lines (memory and I/O). This signal is
active high.
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BALE (O) (buffered)
The 'buffered address latch enable' signal is provided by the Bus Controller and is
used to latch valid addresses and memory decodes from the microprocessor. It is
available to the I/O channel as an indicator of a valid microprocessor or DMA
address (when used with 'address enable' signal, AEN). Microprocessor addresses
SA0 through SA23 are latched with the falling edge of BALE. BALE is forced high
(active) during DMA cycles.
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CLK (O)
This is the 8-MHz system 'clock' signal. It is a synchronous microprocessor cycle
clock with a cycle time of 125 nanoseconds. The clock has a 50% duty cycle. This
signal should be used only for synchronization. It is not intended for uses requiring a
fixed frequency.
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-DACK0 through -DACK3, -DACK5, & -DACK6 (O)
-DMA acknowledge signals are used to acknowledge DMA requests. These signals
are active low.
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DRQ0 through DRQ3, DRQ5, DRQ6 (I)
The 'DMA request' signals are asynchronous channel requests used by peripheral
devices and a microprocessor to gain DMA service (or control of the system). They