Specifications

Connectors
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A10 SD7 A25 DRQ3 A40 SA21 A54 SA1
A11 SD5 A26 DRQ2 A41 SA19 A55 +5V
A12 (unused) A27 DRQ1 A42 SA17 A56 +5V
A13 SD3 A28 DRQ0 A43 TC A57 -RESETIN
A14 SD1 A29 -DACK6 A44 SA15 A58 (unused)
A15 IRQ15 A30 -DACK5
B Row:
Pin Signal Pin Signal Pin Signal Pin Signal
B1 GND B16 GND B31 -SMEMW B45 SA12
B2 (reserved) B17 IRQ9 B32 -SMEMR B46 (key)
B3 GND B18 IRQ6 B33 GND B47 (key)
B4 GND B19 IRQ4 B34 -MEMW B48 SA10
B5 SD14 B20 IRQ3 B35 -MEMR B49 SA8
B6 SD12 B21 -RSTDRV B36 BALE B50 GND
B7 SD10 B22 GND B37 CLK B51 SA6
B8 GND B23 IOCHRDY B38 GND B52 SA4
B9 SD8 B24 -0WS B39 SA22 B53 SA2
B10 SD6 B25 -IOCS16 B40 SA20 B54 SA0
B11 SD4 B26 -MEMCS16 B41 SA18 B55 GND
B12 GND B27 -REFRESH B42 SA16 B56 GND
B13 SD2 B28 GND B43 GND B57 -EXTSMI
B14 SD0 B29 -IOW B44 SA14 B58 GND
B15 IRQ14 B30 -IOR
EXM Expansion Connector Signals
The signal definitions below are listed in alphabetical order. Signal definitions
preceded by a

are copied from the IBM AT Technical Reference Manual. Some
liberties have been taken to correct the definitions for use with the Intel386 SL chip
set and an 8 MHz bus speed.

-0WS (I)
The 'zero wait state' signal tells the microprocessor that it can complete the present
bus cycle without inserting any additional wait cycles. In order to run a memory
cycle to a 16-bit device without wait cycles, 0WS is derived from an address decode
gated with a Read or Write command. In order to run a memory cycle to an 8-bit