Specifications

Connectors
EPC-100 Hardware Reference C-11
CompactPCI J2 Connector
*
Pin A B C D E F
44 USR USR USR USR USR GND
45 USR USR USR USR USR GND
46 USR USR USR USR USR GND
47 USR USR USR USR USR GND
× Notes:
1. This diagram defines the pinout from the front of the system chassis. All pins are medium length
(level 2) except C16 and D15 which are long (level 3) and short (level 1), respectively. The V(I/O)
signals are either 5V or 3.3V, depending on the system implementation.
2. Pin D15 (short, level 1) is used as BD_SEL# for hot-swap capable boards.
3. Pin C16 (long, level 3) is used for early power to hot-swap capable boards for controlling the buffer
logic.
4. Pin D21 is defined as GND for 33MHz backplanes. Use of this signal in 66MHz systems will be as
a bussed signal to all slots.
5. Rows 26-28 are only implemented on the system board.
6. C27 is grounded at the system slot only. Remaining slots leave C27 unconnected.
7. System slot adapters that do not support seven REQ#/GNT# signals must provide a mechanism to
connect any of the Peripheral Slots 2-8 that may need arbitration service depending on the adapter
installed.