Specifications

Chipset and I/O Map
EPC-100 Hardware Reference A-9
ENIE ENUM# interrupt enable. If 1, the cPCI signal ENUM# is allowed to
generate a hotswap event which will generate an interrupt (if the
watchdog interrupt is also disabled). If 0, no hotswap events are
signaled. Power up and reset state: 0.
ENEV Read only bit that indicates a hotswap (ENUM#) event occurred. A
high indicates a hotswap event occurred. Any write to I/O locations
8150-815Fh will reset this bit. Power up and reset state: 0.
WDEV Read only bit that indicates a watchdog event occurred. A high
indicates a watchdog event occurred. Any write to I/O locations
8150-815Fh will reset this bit. Power up state: 0. Reset state: the
state of the bit before reset.
WDIE If set, this bit causes a warm reset on a watchdog event. If reset, this
bit causes an interrupt on a watchdog event. Power up and reset
state: 0.
WDTV Watchdog timer value. If not disabled, the watchdog timer is allowed
to generate a watchdog event which will generate an interrupt or a
warm reset depending on the state of the WDIE bit. If disabled, no
watchdog events are signaled. A write to this register setting the
timer length to a value (other than the disabled setting) will reset the
watchdog counter to zero so that an inadvertent watchdog event does
not occur sooner than expected after enabling the watchdog timer.
This field produces the following time-out values:
Bit 1, Bit 0 Watchdog Timer Length
0,0 Disabled
0,1 8.2 seconds
1,0 128 ms
1,1 1.02 seconds
Notes: A write of the this register has a side effect of resetting the watchdog
timer and the watchdog event indication register (bit 3) and the
hotswap indication register (bit 4). Please refer to the Watchdog
Timer section of Chapter 4, Theory of Operation for more
information about the watchdog timer.