Specifications

Chipset and I/O Map
EPC-100 Hardware Reference A-2
First (8-bit) DMA controller (cont’d)
I/O Addr Functional group Usage
00D Temporary register (R)
Master clear (W)
00E Clear mode reg counter (R)
Clear all DMA req mask(W)
00F All DMA request mask
First Interrupt controller
020 Interrupt controller 1 Port 0
021 Port 1
Counter-Timer functions
040 Timer Counter 0
041 Counter 1
042 Counter 2
043 Control (W)
Keyboard Port
060 Keyboard controller Data I/O register
061 NMI status PIIX3
064 Keyboard controller Command/status register -
resets IRQ1 and 12/M