Specifications

Chipset and I/O Map
EPC-100 Hardware Reference A-1
Appendix A - Chipset and
I/O Map
Introduction
This section contains the port I/O addresses for the address-mapped devices in the
EPC-100. As is standard for the ISA bus, the A[15:0] bits are decoded for the
0200h-03FFh range and A[15] and A[9:0] are decoded for addresses above 8000h.
Table A-1. I/O Address Mapping for the EPC-100
First (8-bit) DMA controller
I/O Addr Functional group Usage
000 DMA Channel 0 address
001 Channel 0 count
002 Channel 1 address
003 Channel 1 count
004 Channel 2 address
005 Channel 2 count
006 Channel 3 address
007 Channel 3 count
008 Command/status
009 DMA request
00A Command register (R)
Single-bit DMA req mask(W)
00B Mode
00C Set byte pointer (R)
Clear byte pointer (W)