Specifications

Theory of Operation
EPC-100 Hardware Reference 4-9
The BIOS initialization software copies the ROM contents into DRAM (a process
called shadowing) at addresses E0000h-FFFFFh. The VGA BIOS is copied into
C0000h-C7FFFh of DRAM. After copying into these areas, the BIOS write-protects
them. Subsequent writes to these areas complete successfully but do not alter the
data in DRAM.
There are two parameter blocks, each 8KB in size, used for BIOS code.
CMOS Save and Restore (CSR)
CMOS memory is backed up to and restored from Main Block 1 of the FBD as
determined by the settings in the BIOS Setup Exit Menu. This allows you to save
your settings to nonvolatile flash memory and to specify the conditions under which
CMOS is to be restored from the FBD. For more information, see the Exit Menu
section of Chapter 3 - BIOS Configuration.
Ethernet Controller
The EPC-100 implements 10/100BaseT Ethernet communications by using the DEC
21143-TA Ethernet Controller chip coupled to a QSI 6611 Physical Interface (PHY)
chip that provides wave shaping and line filtering for both 10- and 100-Mbps
operation, adaptive equalization, baseline wander compensation, 10/100 switching,
and clock generation and recovery. The 21143 chip interfaces to the 32-bit PCI bus
and the QS6611 provides the line driver and receiver for a 10BASE-T and
100BASE-TX Fast Ethernet connection to Category 5 unshielded twisted-pair cable
via an RJ45 connector. 10BASE2 is supported through a BNC connector on the front
panel.
This controller uses PCI INTB and REQ0/GNT0. It is configured through the PCI
Configuration Space.
The Ethernet driver for Windows NT/4.0 is supplied by Digital Equipment
Corporation and is supplied on a separate floppy diskette.
Product: DC21X4.SYS
Software revision: 4.15
Document release date: 1-6-97