Specifications

Theory of Operation
EPC-100 Hardware Reference 4-8
BIOS ROM and ROM Shadowing
The EPC-100 utilizes a Flash Boot Device (FBD) as its BIOS ROM. The BIOS
ROM is mapped into the top of the processor’s 32-bit address space. The BIOS
consists of a 16 KByte boot block and the System BIOS in the 96KB Main block and
both 8KB parameter blocks. The layout is described in Figure 4-2.
Physical Address Device Offset
FFFFFFFFh Boot Block 7FFFFh
FFFFC000h
16 KB
BIOS Recovery Code 7C000h
Parameter Block 2 7BFFFh
FFFFA000h
8 KB
System BIOS 7A000h
Parameter Block 1 79FFFh
FFFF8000h
8 KB
System BIOS 78000h
FFFE0000h
Main Block 4
96 KB
System BIOS, PCI BIOS
Plug n Play BIOS
77FFFh
60000h
FFFC0000h
Main Block 3
128 KB
User Extensions (88KB)
Manufacturing BIOS (8KB)
SCSI BIOS (32KB)
5FFFFh
40000h
FFFA0000h
Main Block 2
128 KB
ESCD (4KB)
3FFFFh
20000h
FFF80000h
Main Block 1
128 KB
CMOS Data (1KB)
1FFFFh
00000h
Figure 4-2. Flash Boot Device Memory