Specifications

Theory of Operation
EPC-100 Hardware Reference 4-6
Interrupt Interrupt Function
IRQ10 unused
IRQ11 unused
IRQ12 Mouse
IRQ13 Numeric coprocessor FERR# (internal PIIX3 connection)
IRQ14 Primary IDE
IRQ15 unused (MIRQ0 for secondary IDE)
NMI PIIX3 when SERR# or IOCHK# is asserted (software controlled)
SMI Power management / Watchdog Timer Event.
PIRQA CompactPCI Bus
PIRQB Ethernet & CompactPCI Bus
PIRQC SCSI & CompactPCI Bus
PIRQD USB & CompactPCI Bus
Note that PIRQ[A-D] correspond directly to the PCI interrupts INT[A-D]. The software may
steer these interrupts to any of the 11 interrupts (IRQ[15,14, 12-9, 7-3]) using the MBIRQx
Route Control Register. Note also that the secondary IDE channel is assigned to MIRQ0 by
the PIIX3 (when not using the APIC, as on EPC-100).
Table 4-3. Interrupt Usage.
Watchdog Timer
The watchdog timer is a binary counter which, upon overflow, will signal a watchdog
timer event. The counter will cause a watchdog event after 128 ms, 1.02 second or
8.2 seconds (depending on the value of WDTV, bits 0 and 1 in register 8150h) if the
application software does not reset the timer by writing to I/O location 8150h before
the set time passes. An I/O write to address 8150h resets the counter.
If WDTV (bits 1 and 0 of register 8150h) are nonzero, the following occurs in
response to a time-out event: The watchdog event register is set. If WDIE (bit 2 of
register 8150h) is zero, IRQ9 is taken high to signal a watchdog time-out via
interrupt. If WDIE (bit 2 of register 8150h) is set, a local “warm” hardware reset
occurs. This reset clears the WDIE bit removing the reset condition. When exiting a
hardware reset condition, the BIOS can check the WDEV bit. If this bit is set, then a