Specifications

Theory of Operation
EPC-100 Hardware Reference 4-2
EIDE Controller consisting of two master and two slave drive controllers
System BIOS implemented as a Flash ROM supporting BIOS extensions
Block Diagram
Figure 4-1 shows the division and interconnection of EPC-100 functions. These are
described below.
Processor Module Daughterboard
An Intel Pentium processor (with integral FPU) runs at 100, 133, 166, or 200 MHz.
The processor, the TXC system controller, and the L2 cache all operate on a
60/66MHz local bus. The PCIbus runs at half the local bus speed (30/33MHz) and
the ISA bus runs at one quarter the PCI bus speed (7.5/8.25 MHz).
Cache Memory
A second-level (L2) write-back 256 or 512KB main-memory cache is implemented
by the Intel 82430HX chipset’s TXC system controller.
Main System Memory
Main memory is implemented as SODIMM 72-pin socketed 3.3 volt DRAM. The
main memory controller supports up to 256MB of 60 or 70 ns Fast Page Mode or
EDO DRAM in two dual 72-pin SODIMM sockets. The CPU memory bus is 64 bits
wide, so the SODIMM sockets must be populated with identical pairs of 32 bit
DRAM modules. The TXC controller generates all of the required control signals,
such as RAS#, CAS#, and WE#, as well as the multiplexed addresses for the DRAM
array.