Specifications

BIOS Configuration
EPC-100 Hardware Reference 3-19
8-bit I/O Recovery
This option selects the number of ISAbus SYSCLKs to be inserted by the chipset
between 8-bit back-to-back I/O accesses. Increasing the number of clocks decreases
I/O performance but may allow slow devices to be accessed properly. This option
can range from 3.5 through 11.5 SYSCLKs in 1 SYSCLK increments. The default is
“4.5” SYSCLKs.
16-bit I/O Recovery
This option selects the number of ISAbus SYSCLKs to be inserted by the chipset
between 16-bit back-to-back I/O accesses. Increasing the number of clocks decreases
I/O performance but may allow slow devices to be accessed properly. This option
can range from 3.5 through 7.5 SYSCLKs in 1 SYSCLK increments. The default is
“4.5” SYSCLKs.
IRQ 12 used by
This option selects the routing of IRQ12. For systems without a PS/2 mouse, this
option may be set to “PCI bus” to allow an ISAbus peripheral to use this interrupt
line. Systems using a PS/2 mouse must have this option set to “PS/2 Mouse” for the
mouse to operate correctly. Since the EPC-100 supports the PS/2 mouse connector,
the default is “PS/2 Mouse”.
ECC/Parity Config
This option configures the DRAM controller to use no parity (“Disabled”), parity
(“Parity”), or Error Checking and Correction (“ECC”) when accessing DRAM. Use
of parity or ECC may improve system reliability since DRAM errors are likely to be
detected by the chipset. Use of ECC allows for the detection of single and dual bit
errors and the correction of single bit errors during DRAM reads. The parity and
ECC selections require that all SODIMMs be x36 instead of x32. The “Disabled”
selection can use either x32 or x36 SODIMMs. The default is “Disabled”.