Specifications

Product Description
EPC-100 Hardware Reference
1-5
about PICMG and the cPCI standard consult the PICMG website at
http://www.picmg.org.
cPCI Device Interface
The EPC-100 implements a 32 bit CompactPCI system slot board capable of driving
seven CompactPCI slots. A DEC 21150 PCI-PCI bridge chip is used to interface
between the base board’s local PCI bus and the CompactPCI bus. The bridge chip
controls a layer of buffers between it and the CompactPCI bus and has a glueless
interface to the local PCI bus. PCI interrupts (INT[A:D]#) are directly handled by
the CPU sub-module’s interrupt controller.
The CompactPCI bus interface uses the standard 2 mm-pitch, 7-row Hard Metric
connector. This connector has a 7 column by 47 row array of pins divided into two
groups corresponding to the physical implementation. The two outside columns are
used as a ground shield for EMI protection. Of the remaining columns, J1 pins 1-25
provide 32 bit PCI and connector keying implemented as one connector. J2 pins 1-
22 provide 64 bit support, clocking, and arbitration with a portion reserved for future
use.
The CompactPCI bus interface includes the following features:
•
The DEC 21150 PCI-PCI bridge provides full CompactPCI bus System
Controller (Slot 1) features including bus arbitration, signal pull-ups, device
configuration, idle bus parking, and clock generation and buffering.
•
Support for CompactPCI Signal Additions (to the PCI specification):
push-button reset, power supply status, system slot identification, and separate
primary and secondary interrupts.
•
The EPC-100 presents a double load on each CompactPCI bus signal as allowed
by the CompactPCI standard.