Specifications

Troubleshooting and Error Messages
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Page 72
BIOS Checkpoints
The Phoenix PicoBIOS in the EPC-30 writes a number of POST checkpoint
codes to I/O port 80h just before each checkpoint executes. Table 5-2
describes these checkpoint codes and instructions.
NOTE: The POST checkpoint codes generally execute in the order the table
shows. The codes may not execute in the exact order in the table.
Beep Code POST CODE Checkpoint Description
02h Verify Real Mode
04h Get CPU type
06h Initialize system hardware
08h Initialize chipset registers with initial POST values
09h Set in POST flag
0Ah Initialize CPU registers
0Ch Initialize cache to initial POST values
0Eh Initialize I/O
10h Initialize Power Management
11h Load alternate registers with initial POST values
12h Jump to UserPatch0
14h Initialize keyboard controller
1-2-2-3 16h BIOS ROM checksum
18h 8254 timer initialization
1Ah 8237 DMA controller initialization
1Ch Reset Programmable Interrupt Controller
1-3-1-1 20h Test DRAM refresh
1-3-1-3 22h Test 8742 Keyboard Controller
24h Set ES segment register to 4 GB
28h Autosize DRAM
2Ah Clear 512 KB base RAM
1-3-4-1 2Ch Test 512 KB base address lines
1-3-4-3 2Eh Test 512 KB base memory
32h Test CPU bus-clock frequency
37h Reinitialize the chipset
38h Shadow system BIOS ROM
39h Reinitialize the cache
3Ah Autosize cache
Table 5-2. POST Checkpoint Codes.