Specifications

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EPC-30 Hardware Reference
Page 39
The RFA access may be implemented through a 16K memory window in the
processor’s address space. This is useful for real mode operating systems
such as DOS. The processor’s CS6 is used in addressing the RFA along with
additional address bits from an upper address register. A 10-bit upper
address register (only eight bits are used) resides on the ISA data bus which
is accessed using CS2 from the R380EX. This memory window is
programmed using the processor’s and R380EX’s chip selects. To access
the RFA in this manner, the BIOS needs to be configured to select IO
mapped page operation of the RFA. The factory-shipped implementation of
Phoenix PICO Flash uses D4000h as the window address and 380h as the
page register.
The RFA may also be mapped as linear high memory to 48 MBytes, or
3000000H. In this mode of operation, the 386EX CS6 chip select is used
alone to select the device in its entirety. To select this method of operation,
change the BIOS screen in the Advanced Menu to select linear memory
addressing for the RFA. The BIOS initially programs the RFA at 48MB
(3000000H).
A resistor setting is used to provide control of the programming voltage to
the flash device. A separate resistor selects the source of the write enable
signal into the part, either the R380 flash write or 386EX ~WR signal. A
programmable pin on the 386 EX (configurable in the BIOS setup) can force
the RFA to operate in a byte-wide mode (as opposed to 16-bit operation).