Specifications

EPC-30 Hardware Reference

Page 36

Table 3-1. Functional Unit Summary.

DRAM Interface/Bus Control

The processor-to-board interface supporting DRAM and bus control is

managed by the RadiSys R380EX memory/bus controller (U20). The

R380EX is designed specifically for use with the Intel386 EX processor and

provides the support the Intel386 EX requires for DRAM, flash or EPROM

control, reset synchronization, ready generation, data bus transceiver control,

and the ISA bus.

The R380EX fast page mode, zero wait state DRAM controller includes

address multiplexers, page hit logic for address pipelining, RAS and CAS

generation and CAS before RAS DRAM refresh control. The DRAM

controller provides support for 1, 2, 4, 8, and 16 MB SIMMs.

Functionally, the R380EX provides control signals for flash memory, the

real time clock, IDE interface, and the keyboard/mouse controller. It also

generates a clock synchronized RESET signal for the Intel386 EX, and the

READY# signal for non-local bus access cycles. The R380EX also generates

I/O read/write, memory read/write, address latch enable and other signals.

A data buffer control signal prevents data bus contention that could result

from direct use of the Intel386 EX RD# signal as the output enable for

external devices.

Memory

The EPC-30 supports 70ns fast page mode (FPM) or extended data out

(EDO) DRAM installed in a 72-pin SIMM socket. SIMM memory may be

installed to support from 1MB up to 16MB of DRAM. Physically, the EPC-

30 has only one SIMM socket. The second module is the soldered-down

DRAM (1MB, 2MB or 4MB configuration). After power on reset, the BIOS

will find and size memory present in the system. The EPC-30 does not

support parity DRAM.

To improve the performance of the BIOS that is initially contained in a 16-

bit wide flash EPROM, the main BIOS and, optionally, the video BIOS will

be shadowed in the DRAM.

Use of a double-sided SIMM with soldered-down DRAM is not

recommended due to RAS line restrictions.

The DRAM controller’s address pipelining supports zero wait state read and

write cycles to and from the DRAM. With a two-bank, symmetrical