Specifications

Page D-11

Reflashing the FBD

This appendix describes how to reflash the Intel Flash Boot Device (FBD) which

contains the EPC-30 System BIOS and, optionally, ROM BIOS extensions. Appendix

D first presents information about the BIOS structure, then defines the reflashing

processes and describes how to accomplish them.

About the Flash Boot Device

The EPC-30 employs Phoenix PicoBIOS version 4.05 implemented as a

flash BIOS using the 2 MB (256 KB) Intel PA28F200BV-T SmartVoltage

Boot Block Flash Device. The Flash Boot Device (FBD) contains a 16 KB

boot block which holds the BIOS initializing and recovery code.

Main block #1 contains a Cirrus Logic video BIOS extension, an 8KB

RadiSys manufacturing BIOS, the PicoCard BIOS extension, and the

PicoFlash BIOS extension.

The system BIOS code image resides in main block 2.

Parameter block 1 contains the System BIOS.

Parameter block 2 is unused.

See Figure D-1

Figure D-1. EPC-30 FBD Memory Map.

The FBD is memory addressed and resides in the last 256KB of physical

address space at addresses 3F80000h through 3FFFFFFh. The System BIOS

is shadowed and write-protected at 0E0000H through 0FFFFFH (128KB)

upon any system reset (warm boot, shutdown, power-up or "reset signal"

reset).

The boot block, main blocks, and parameter blocks are protected against

accidental writes. Three register bits in the R380EX’s BIOS Control

further protected by a jumper which must also be in place before writes to

the boot block can take place.

A "force recovery" signal is provided on the misc. expansion header that is

readable by the boot block and can force the boot block to initiate a BIOS

recovery sequence. This signal can force the boot block to initiate a recovery

sequence should the other methods of initiating the sequence become

inaccessible (for example, the System BIOS becomes corrupted such that the

system cannot boot to the OS). The value of the signal is readable by the

R380EX using the SMI Control/Status Register.